Merge pull request #6 from AUDIY/Release_v1

Release v1
AUDIY · Jan 19, 2025 · d238e8c · d238e8c
2 parents d59cb9f + 29ccf76
commit d238e8c
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Showing 17 changed files with 33 additions and 32 deletions.
diff --git a/01_DPRAM_CONT/DPRAM_CONT.v b/01_DPRAM_CONT/DPRAM_CONT.v
@@ -3,9 +3,9 @@
 *
 * Simple Dual Port RAM Controller to operate as Ring-Buffer.
 *
-* Version: 0.23
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * Port
 *   Input

diff --git a/01_DPRAM_CONT/DPRAM_CONT_TB.v b/01_DPRAM_CONT/DPRAM_CONT_TB.v
@@ -3,9 +3,9 @@
 *
 * Test Bench for DPRAM_CONT.v
 *
-* Version: 0.23
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * License
 --------------------------------------------------------------------------------

diff --git a/02_DATA_BUFFER/DATA_BUFFER.v b/02_DATA_BUFFER/DATA_BUFFER.v
@@ -3,9 +3,9 @@
 *
 * Input DATA Buffer with RAM
 *
-* Version: 0.13
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * Port
 *   Input

diff --git a/02_DATA_BUFFER/DATA_BUFFER_TB.v b/02_DATA_BUFFER/DATA_BUFFER_TB.v
@@ -3,9 +3,9 @@
 *
 * Test bench for DATA_BUFFER.v
 *
-* Version: 0.12
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * License
 --------------------------------------------------------------------------------

diff --git a/02_DATA_BUFFER/SDPRAM_SINGLECLK.v b/02_DATA_BUFFER/SDPRAM_SINGLECLK.v
@@ -3,9 +3,9 @@
 *
 * Simple Dual-Port RAM (Single Clock)
 *
-* Version: 0.11
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/21
+* Date   : 2025/01/20
 *
 * Port
 *   Input

diff --git a/03_SPROM_CONT/SPROM_CONT.v b/03_SPROM_CONT/SPROM_CONT.v
@@ -3,9 +3,9 @@
 *
 * Single Port ROM Controller to Output Filter Coefficients.
 *
-* Version: 0.18
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * Port
 *   Input

diff --git a/03_SPROM_CONT/SPROM_CONT_TB.v b/03_SPROM_CONT/SPROM_CONT_TB.v
@@ -3,9 +3,9 @@
 *
 * Test Bench for SPROM_CONT.v
 *
-* Version: 0.18
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * License
 --------------------------------------------------------------------------------

diff --git a/04_FIR_COEF/FIR_COEF.v b/04_FIR_COEF/FIR_COEF.v
@@ -3,9 +3,9 @@
 *
 * FIR Coefficients ROM.
 *
-* Version: 0.16
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * Port
 *   Input

diff --git a/04_FIR_COEF/FIR_COEF_TB.v b/04_FIR_COEF/FIR_COEF_TB.v
@@ -3,9 +3,9 @@
 * 
 * Test Bench for FIR_COEF.v
 *
-* Version: 0.15
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * License
 --------------------------------------------------------------------------------

diff --git a/04_FIR_COEF/SPROM.v b/04_FIR_COEF/SPROM.v
@@ -3,9 +3,9 @@
 *
 * Single-Port ROM
 *
-* Version: 0.10
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/10
+* Date   : 2025/01/20
 *
 * Port
 *   Input

diff --git a/05_MULT/MULT.v b/05_MULT/MULT.v
@@ -3,9 +3,9 @@
 *
 * PCM DATA & Digital Filter Multiplier w/ input & output register.
 *
-* Version: 0.15
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * Port
 *   Input

diff --git a/05_MULT/MULT_TB.v b/05_MULT/MULT_TB.v
@@ -3,9 +3,9 @@
 *
 * Test Bench for MULT.v
 *
-* Version: 0.15
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * License
 --------------------------------------------------------------------------------

diff --git a/06_ADD/ADD.v b/06_ADD/ADD.v
@@ -3,9 +3,9 @@
 *
 * Multiplied Data Integrator w/ input & output register.
 *
-* Version: 0.16
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * Port
 *   Input

diff --git a/06_ADD/ADD_TB.v b/06_ADD/ADD_TB.v
@@ -3,9 +3,9 @@
 *
 * Test Bench for ADD.v
 *
-* Version: 0.16
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * License
 --------------------------------------------------------------------------------

diff --git a/07_FIR_x2/FIR_x2.v b/07_FIR_x2/FIR_x2.v
@@ -3,9 +3,9 @@
 *
 * Oversampling FIR Filter Module (Oversampling Ratio: x2)
 *
-* Version: 0.16
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * Port
 *   Input

diff --git a/07_FIR_x2/FIR_x2_TB.v b/07_FIR_x2/FIR_x2_TB.v
@@ -3,9 +3,9 @@
 *
 * Test Bench for FIR_x2.v
 *
-* Version: 0.16
+* Version: 1.00
 * Author : AUDIY
-* Date   : 2023/12/23
+* Date   : 2025/01/20
 *
 * License
 --------------------------------------------------------------------------------

diff --git a/README.md b/README.md
@@ -24,6 +24,7 @@ https://audio-diy.hatenablog.com/entry/FIR_x2_howtouse
 2. FIR filter length must be equals to (MCLK_I frequency)/(Sampling frequency)
 3. Test benches are used on Questa - Intel FPGA Starter Edition. So there are no stop command in them.
 4. This project includes asynchronous design now. The author will try to make this completely synchronous design.
+5. When you use in vivado, memory file(.hex) should be changed to data file(.data). 
 
 ## Verified Devices
 1. Efinix T20F256I4 on Trion T20 BGA256 Development Kit( https://www.efinixinc.com/products-devkits-triont20.html )