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1. Hardware-Accelerator-for-Scaled-Dot-Product-Attention-in-Transformer-Architectures Hardware-Accelerator-for-Scaled-Dot-Product-Attention-in-Transformer-Architectures Public

   Verilog 1

2. AHB-Lite-DMA-controller-for-memory-to-memory-transfer-using-SRAM-slaves AHB-Lite-DMA-controller-for-memory-to-memory-transfer-using-SRAM-slaves Public

   Synthesizable AHB-Lite DMA controller that performs memory-to-memory transfers between two SRAM blocks, supporting single and burst transfers, interrupt-driven completion, and performance monitoring

   SystemVerilog 1

3. 5-Stage-Pipelined-RISC-V-RV32I-Processor-Design 5-Stage-Pipelined-RISC-V-RV32I-Processor-Design Public

   A 32-bit 5-stage pipelined RISC-V (RV32I) processor implemented in SystemVerilog, featuring Instruction Fetch, Decode, Execute, Memory, and Writeback stages with a modular RTL design. Includes a re…

4. APB-AMBA-Protocol-Implementation-in-RTL APB-AMBA-Protocol-Implementation-in-RTL Public

   Complete APB (Advanced Peripheral Bus) RTL implementation in Verilog following ARM AMBA specification. Includes master, slave, decoder modules with comprehensive testbench.

   Verilog 1

5. MRAM-Inspired-Near-Memory-CIM-Accelerator-for-Bitwise-and-Matrix-Operations MRAM-Inspired-Near-Memory-CIM-Accelerator-for-Bitwise-and-Matrix-Operations Public

   This project implements a synthesizable MRAM-inspired compute-in-memory (CIM) accelerator in SystemVerilog. Since true MRAM CIM relies on analog device physics and array-periphery co-design, this w…

6. My-Portfolio My-Portfolio Public

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