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OpenExSys_CoherentCache
OpenExSys_CoherentCache PublicOpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.
SystemVerilog 11
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axi
axi PublicForked from pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog
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