4th-year Electrical & Electronics Engineering Student | Tel Aviv University Specializing in VLSI Design, Computer Architecture, and Digital Systems.

• HDLs & Design: SystemVerilog, Verilog, Vivado, ModelSim, HDLBits
• VLSI & Architecture: RISC-V (Rocket, SonicBOOM), Chipyard, Cadence Virtuoso (Layout, LVS/DRC), Synopsys Euclide (RTL, Logic Synthesis)
• Software: Python, C, C++, MATLAB, Assembly
• Hardware: FPGA (Artix-7), PCB Design (OrCAD, Allegro), GNSS (U-blox)
• Protocols: AXI, I2C, SPI, UART

Configuring Rocket and SonicBOOM cores via Chipyard. Implementing hardware-accelerated matrix multiplication on Artix-7 FPGAs.

Designed and verified a 4-port packet switch in SystemVerilog, featuring custom arbitration logic and FIFO buffering.

Designed a high-gain two-stage OTA using IBM 130nm process in Cadence Virtuoso. Optimized for stability and Miller compensation.

Designed and physically implemented a synchronous 4-bit ALU using a Kogge-Stone prefix adder. Performed multi-voltage timing characterization (0.9V / 1.2V), derived Fmax up to 3.31 GHz, and completed DRC/LVS-clean standard-cell layout.

• LinkedIn: linkedin.com/in/asafalber
• Email: asaf.alber@gmail.com