Fix illegal signal names generated from real literals #757
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If a real literal was small enough to use E notation with a negative exponent, that negative sign would appear in signal names derived from that expression, which is illegal for both Verilog and Bluesim. We were eliminating decimal points from numbers, but failing to remove negative signs. Instead of removing them, however, we now replace them (with "d" and "neg") so that the value in the name is not misinterpreted.
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This was accidentally missing from the new jobs for testing GHC versions
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For signals without source names, BSC constructs a name based on the assigned expression. If the expression contains a number, that number appears in the name. BSC filters out a few characters, such as decimal points (
.) but was not eliminating negative signs (-) which can show up if aRealliteral is small enough that E notation with a negative exponent is used. In that case, BSC was generating a signal name with a negative sign in it, which is not legal for names in Verilog or Bluesim. In the Verilog backend, such names are probably inlined anyway, but I ran into a situation ($displayof aRealvalue) where the signal survived in Bluesim and caused a C++ compilation failure.Filtering out the decimal point causes a real number to look like a large integer, which was confusing when I saw such signal names. So instead of fixing this bug by adding
-to the list of characters to be removed, I changed BSC so that it replaced decimal points bydand negative signs byneg, so that the value in the name is not misinterpreted.