Support methods with multiple output ports

[krame505]

This is nowhere close to finished, but I've started working on adding support for methods with multiple output ports, as an extension of my previous work on input port splitting in #729¹. The high-level idea is to make the port-splitting type classes allow the creation of wrapper methods that return tuples of Bit values, make AConv understand Bit tuples as synthesizable, and plumb this all the way through the rest of the compiler. AIDef and AIActionValue are changed to contain multiple ADefs, and AMethCall and AMethValue now contain an index of which output port's value is being accessed from the method.

I've gotten quite a ways into implementing this - bsc mostly compiles except for AState.hs, which I am still trying to make sense of. The Bluesim, lambda calculus and SAL (what is that?) back ends are currently stubbed out and give an error when encountering AIDef/AIActionValue with multiple ADefs. I think we only really care about supporting multiple output ports for the Verilog and Bluesim backends, the others may be left as future work.

One question I have for @quark17 is what is the most straightforward path to make Bluesim support methods with multiple output ports - should we generate structs for these methods' sim functions to return, containing the output port values? Or just return all the port values as a big bit vector and do the appropriate slicing?

This is still a draft with much debugging to do, but I would appreciate any early feedback.

Footnotes

1. I'm not sure how to make that branch show up as the base of this pull request, since the port splitting branch is on my fork of the bsc repo, so all those changes show up here as well. You can see the diff with only my new output port splitting changes here. ↩

[krame505]

After further discussion with @nanavati, it seems that putting a port number in AMethCall/AMethValue is not the way to go, since we still want the scheduler to work at the level of methods and not ports, and for disjointness testing we want to have AExprs that refer to particular methods, not to ports.

So instead I am going to add a notion of tuple types and selectors to the ASyntax, such that a call to a multi-output method will be converted to a tuple selection on an AMethCall/AMethValue that just has the method id, not the output port id.

[krame505]

Update, I have Verilog and Bluesim working for methods with multiple output ports.

[krame505]

For the sake of reviewing these output port splitting changes before #729 is merged, I created krame505#1.

[krame505]

As I feared, rebasing this on top of the genwrap branch proved infeasible - so I went ahead and squashed the changes here and cherry-picked them on top of that branch.