Update CSR/SCR register file to use a BRAM #15
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This adds a BRAM in CSR_RegFile_MSU so that CSRs and SCRs can eventually be stored in there, saving area on FPGA. The BRAM is correctly inferred in Quartus. Currently, only the uncommented registers in ISA_Decls_CSR use the BRAM, and these have not yet been removed from the CSR_RegFile_MSU so for now they are duplicated and area usage is higher.
This commit moves the SCRs that had not yet been moved into the BRAM. It also does some more optimisations, including: - Get rid of an unnecessary access_permitted port - Move the actual CSR reading to the start of the cycle after the request is made (to improve fmax) - Get rid of rg_csr_scr_address in CPU.bsv since we can just work it out from the trap information - Move tselect, tdata1, tdata2, tdata3 to the SCR BRAM - Clean up BRAM reset logic to remove an unnecessary cycle from the reset - Clean up various sections of commented code Lastly this commit adds a couple of comments to the CSR Regfile
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This updates the CSR/SCR register file to use a BRAM to hold all SCRs and some CSRs. It changes the register file to use a request/response protocol rather than the method that was used before.
CSR/SCR accesses have to be registered the cycle before they are required. In most cases this is easily doable without major changes, since the CSR or SCR address is available in that earlier cycle. However there are two cases in which this requires some significant changes: reading CSRs in Debug mode requires an extra cycle, and xRET instructions require an extra cycle.
Let me know what needs to be improved on.
Edit: One thing is that I'm not sure how the debug interface is used so I haven't been able to test it.