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Merge branch 'hmka2' into freertos-update
2 parents b529760 + 6140ba6 commit 0a864a9

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11 files changed

+779
-162
lines changed

11 files changed

+779
-162
lines changed

Jenkinsfile

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -93,11 +93,11 @@ pipeline {
9393
environment {
9494
PYTHONDONTWRITEBYTECODE = '1'
9595
}
96-
post {
97-
failure {
98-
mail(to: '[email protected]', subject: "Failed Pipeline: ${currentBuild.fullDisplayName}", body: "Something is wrong with ${env.BUILD_URL}")
99-
}
100-
}
96+
//post {
97+
// failure {
98+
// mail(to: '[email protected]', subject: "Failed Pipeline: ${currentBuild.fullDisplayName}", body: "Something is wrong with ${env.BUILD_URL}")
99+
// }
100+
// }
101101
options {
102102
checkoutToSubdirectory('src')
103103
timestamps()

pycheribuild/config/chericonfig.py

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -328,6 +328,17 @@ def __init__(self, loader, action_class: "type[CheribuildActionEnum]") -> None:
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group=loader.cross_compile_options_group,
329329
help="The floating point/SIMD mode to use for building AArch64 programs",
330330
)
331+
332+
self.riscv_baremetal_hardfloat = loader.add_bool_option("riscv-baremetal-hardfloat", default=False,
333+
group=loader.cross_compile_options_group,
334+
help="Use hard floating point ABI for building CHERI-RISC-V programs")
335+
self.riscv_cheri_rvc = loader.add_bool_option("riscv-cheri-rvc", default=False,
336+
group=loader.cross_compile_options_group,
337+
help="Build CHERI-RISC-V projects with compressed CHERI instructions support")
338+
self.riscv_cheri_gprel = loader.add_bool_option("riscv-cheri-gprel", default=False,
339+
group=loader.cross_compile_options_group,
340+
help="Build CHERI-RISC-V libs with gprel ABI for CheriFreeRTOS compartmentalization")
341+
331342
self.crosscompile_linkage = loader.add_option(
332343
"cross-compile-linkage",
333344
default=Linkage.DEFAULT,

pycheribuild/config/compilation_targets.py

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -277,9 +277,21 @@ def essential_compiler_and_linker_flags_impl(
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result.append("-mabi=" + cls.get_riscv_abi(xtarget, softfloat=softfloat))
278278
result.append("-mrelax" if _linker_supports_riscv_relaxations(instance.linker, config) else "-mno-relax")
279279

280+
softfloat = not config.riscv_baremetal_hardfloat
281+
280282
if cls.is_baremetal() or cls.is_rtems():
281283
# Both RTEMS and baremetal FreeRTOS are linked above 0x80000000
282-
result.append("-mcmodel=medany")
284+
result.append("-mcmodel=medium")
285+
286+
# Enable generating CHERI-RISC-V compressed instructions
287+
if config.riscv_cheri_rvc:
288+
if xtarget.is_cheri_hybrid() or xtarget.is_cheri_purecap():
289+
result.append("-mxcheri-rvc")
290+
291+
if config.riscv_cheri_gprel:
292+
if xtarget.is_cheri_purecap():
293+
result.append("-cheri-cap-table-abi=gprel")
294+
283295
elif xtarget.is_aarch64(include_purecap=True):
284296
fp_simd_option = AArch64FloatSimdOptions.SOFT if softfloat else config.aarch64_fp_and_simd_options
285297
march_suffix = fp_simd_option.clang_march_flag()

pycheribuild/processutils.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -229,7 +229,7 @@ def keep_terminal_sane(gave_tty_control=False, command: Optional[list] = None):
229229
finally:
230230
# Can seemingly get unwanted SIGTTOU's whilst restoring so just ignore
231231
# them temporarily.
232-
with suppress_sigttou(suppress=gave_tty_control):
232+
with suppress_sigttou():
233233
stdin_state.restore()
234234
stdout_state.restore()
235235
stderr_state.restore()

pycheribuild/projects/cross/compiler_rt.py

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -184,10 +184,14 @@ def install(self, **kwargs):
184184
if self.target_info.is_rtems():
185185
self.move_file(self.install_dir / "lib/rtems5" / libname, self.install_dir / "lib" / libname)
186186
elif self.target_info.is_baremetal():
187-
self.move_file(self.install_dir / "lib/baremetal" / libname, self.real_install_root_dir / "lib" / libname)
188-
self.create_symlink(
189-
self.install_dir / "lib" / libname, self.install_dir / "lib/libgcc.a", print_verbose_only=False
190-
)
187+
if self.config.riscv_cheri_gprel:
188+
gprel_libname = "libclang_rt.builtins-" + self.triple_arch + "-gprel.a"
189+
self.move_file(self.install_dir / "lib/baremetal" / libname, self.real_install_root_dir / "lib" / gprel_libname)
190+
else:
191+
self.move_file(self.install_dir / "lib/baremetal" / libname, self.real_install_root_dir / "lib" / libname)
192+
self.create_symlink(
193+
self.install_dir / "lib" / libname, self.install_dir / "lib/libgcc.a", print_verbose_only=False
194+
)
191195

192196

193197
class BuildUpstreamCompilerRtBuiltins(BuildCompilerRtBuiltins):

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