Backport priv 1.12 changes#294
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commit a46d410 upstream Currently, the privileged specification version are defined in a complex manner for no benefit. Simplify it by changing it to a simple enum based on. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220303185440.512391-2-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
commit 3a4af26 upstream Add the definition for ratified privileged specification version v1.12 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220303185440.512391-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
commit a4b2fa4 upstream To allow/disallow the CSR access based on the privilege spec, a new field in the csr_ops is introduced. It also adds the privileged specification version (v1.12) for the CSRs introduced in the v1.12. This includes the new ratified extensions such as Vector, Hypervisor and secconfig CSR. However, it doesn't enforce the privilege version in this commit. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220303185440.512391-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> [ Changed CSR function table initialisation to use macros ] Signed-off-by: Stuart Menefy <stuart.menefy@codasip.com>
commit 7100fe6 upstream Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. This commit enforces the privilege version for csrs introduced in v1.12 or after. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220303185440.512391-7-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
commit b1675ee upstream As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220620231603.2547260-6-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> [ Changed CSR function table initialisations to use macros ] Signed-off-by: Stuart Menefy <stuart.menefy@codasip.com>
commit 598ca83 upstream The minimum priv spec versino for mcountinhibit to v1.11 so that it is not available for v1.10 (or lower). Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220628101737.786681-3-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> [ Changed CSR function table initialisations to use macros ] Signed-off-by: Stuart Menefy <stuart.menefy@codasip.com>
Add a henvcfg component to struct CPURISCVState. This avoids a conflict when backporting the Zicboz extension.
This is gone in 0.9.6 so guard it with an ifdef
commit 29a9ec9 upstream The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220303185440.512391-6-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> [ Changed CSR function table initialisations to use macros ] Signed-off-by: Stuart Menefy <stuart.menefy@codasip.com>
The Linux kernel parses the ISA extensions from "riscv,isa" DT property. It used to parse only the single letter base extensions until now. A generic ISA extension parsing framework was proposed[1] recently that can parse multi-letter ISA extensions as well. Generate the extended ISA string by appending the available ISA extensions to the "riscv,isa" string if it is enabled so that kernel can process it. [1] https://lkml.org/lkml/2022/2/15/263 Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Suggested-by: Heiko Stubner <heiko@sntech.de> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220329195657.1725425-1-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> (cherry picked from a775398) Signed-off-by: Stuart Menefy <stuart.menefy@codasip.com> (Stuart: Removed extensions which aren't supported yet)
Now we have the ability to handle generic extension names has been added to qemu and Linux, add the CHERI extension strings. Signed-off-by: Stuart Menefy <stuart.menefy@codasip.com>
Add the zcherilevels extension to the isa string if this extension is enabled.
The RISC-V base cache management operation (CBO) ISA extension has been ratified. It defines three extensions: Cache-Block Management, Cache-Block Prefetch and Cache-Block Zero. More information about the spec can be found at [1]. Let's start by implementing the Cache-Block Zero extension, Zicboz. It uses the cbo.zero instruction that, as with all CBO instructions that will be added later, needs to be implemented in an overlap group with the LQ instruction due to overlapping patterns. cbo.zero throws a Illegal Instruction/Virtual Instruction exception depending on CSR state. This is also the case for the remaining cbo instructions we're going to add next, so create a check_zicbo_envcfg() that will be used by all Zicbo[mz] instructions. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230224132536.552293-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> This is a manual backport of upstream commit a939c500793 ("target/riscv: implement Zicboz extension"). Update the extension definition and properties for 6.x. cpu_gpr[] is not used for cheri, use get_gpr to read a register value.
Zicbom is the Cache-Block Management extension defined in the already ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1]. The extension contains three instructions: cbo.clean, cbo.flush and cbo.inval. All of them must be implemented in the same group as LQ and cbo.zero due to overlapping patterns. All these instructions can throw a Illegal Instruction/Virtual Instruction exception, similar to the existing cbo.zero. The same check_zicbo_envcfg() is used to handle these exceptions. Aside from that, these instructions also need to handle page faults and guest page faults. This is done in a new check_zicbom_access() helper. As with Zicboz, the cache block size for Zicbom is also configurable. Note that the spec determines that Zicbo[mp] and Zicboz can have different cache sizes (Section 2.7 of [1]), so we also include a 'cbom_blocksize' to go along with the existing 'cboz_blocksize'. They are set to the same size, so unless users want to play around with the settings both sizes will be the same. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224132536.552293-4-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> This is a manual backport of upstream commit e05da09b7cf ("target/riscv: implement Zicbom extension"). Update the extension definition and properties for 6.x. cpu_gpr[] is not used for cheri, use get_gpr to read a register value. Explain the missing size parameter for probe_access_flags.
Check that the cache block size for cboz is a power of two. The code for aligning the start address to the cache block size requires this. Define a macro, we need the same check for the cbom blocksize.
Check that the cache block size for cbom is a power of two. The code for aligning the start address to the cache block size requires this. Use the existing macro for this check.
Move the code from helper_cbo_zero into do_cbo_zero. The latter can be shared between the cheri and non-cheri cbo zero helpers.
Move some checks out of do_cbo_zero back into helper_cbo_zero. We'll have two different cbo zero helpers for cheri and non-cheri, both of which will call do_cbo_zero to do the actual zeroing. The cheri helper must do things in this order 1.) check if the CSRs permit the cbo.zero 2.) align the address to the cache block size 3.) do cheri checks on the authorizing capability and the aligned address 4.) call do_cbo_zero 1.) and 2.) have to be done in the "upper" cheri/non-cheri helpers. This patch moves them out of do_cbo_zero back into the non-cheri helper. (The cheri helper will be added shortly.)
Add a helper function to emulate cbo.zero on a risc-v cheri system. This helper works in both capability and integer pointer mode. It performs the required cheri checks and passes the cache-block aligned start address to do_cbo_zero, where the memory and the tags are erased. Do the CSR checks first and abort if the cbo.zero instruction is not allowed. Co-authored-by: Alexander Richardson <alexrichardson@google.com>
When we zero the memory region on a cheri system, we have to clear the corresponding tags. mem is a host memory pointer. Obtain its ram block. Protect the block from being unlinked while we use it. Locate the tag memory for this ram block and clear the tags for our region.
Upstream qemu added support for cbo.zero and introduced a helper that receives the address from the rs1 register. In order to support cheri, we added another cbo.zero helper for cheri systems. It receives the (capability or integer) register number. We can then read the register value (in integer pointer mode) or the authorizing capability (in capability pointer mode). This patch modifies trans_cbo_zero to call one of these two helper depending on cheri support.
Co-authored-by: Martin Kaiser <martin.kaiser@codasip.com> Co-authored-by: Paul Buxton <paul.buxton@codasip.com> Co-authored-by: Alexander Richardson <alexrichardson@google.com>
Now qemu has the infrastructure to support privileged spec version 1.12 we can switch to the correct version. Signed-off-by: Stuart Menefy <stuart.menefy@codasip.com>
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