fix(aarch64): shift immhi bits of ADRP to account for immlo#121
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CensoredUsername merged 1 commit intoFeb 11, 2026
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the immlo bits of the ADRP instruction on aarch64 must be shifted by 2, as the bottom two bits are stored in the immhi field. Similarly to how ADR works.
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Thanks! I'll take a look at it. |
Owner
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Looks correct, this also matches how the runtime processes ADRP relocations. Not sure what happened here. The blacklisted test is because the assembler I was using at the time as reference didn't like getting an immediate as the argument for ADRP so I couldn't validate it. Unfortunate that an error snuck in there. I'll rebase this to dev once I'm done with the relocation rework. |
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Author
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Awesome, thanks. Happy to contribute |
Owner
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The changes are live now in v5.0.0, thanks for the contribution! |
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the immlo bits of the ADRP instruction on aarch64 must be shifted by 2, as the bottom two bits are stored in the immhi field. Similarly to how ADR works.
There is also blacklisted
adrpwithin the testcase generator, I am not sure if it's because of this encoding issue or there was some other reason for it, probably worth a second look. (/tools/aarch64_emit_tests.py)I couldn't get the test suite to regenerate on my mac easily, so I didn't check it.