●Wrote the Verilog for GCN modules and verify the functionality; Synthesized the design using Design Compiler and verified the synthesized netlist.
●Performed automatic place-and-route (APR) using Innovus; Post-APR - export GDS, imported the GDS into Virtuoso layout, and performed DRC/LVS on the final layout of the design.completed a low-power GCN module, with end-to-end latency =516ps