RISC-V Processor on DE-1 SoC FPGA

Welcome to the risc-v-on-de1-soc-fpga repository! This project implements a simplified RISC-V processor architecture using Verilog and is deployed on the DE-1 SoC FPGA development board.

Repository Structure

The repository is structured as follows:

• Single Cycle Processor: Contains the implementation of the single-cycle RISC-V CPU and its modules.

• Multi Cycle Processor: Contains the implementation of the multi-cycle RISC-V CPU and its modules.

• Pipelined Processor: Coming soon...

• Images: Visuals, diagrams, and waveform screenshots related to the design and simulation.

• Resources:

  • Digital Design and Computer Architecture RISC-V Edition.pdf
  • Getting Started with FPGAs.pdf
  • Project Plan.pdf

The cpu.v module is the top-level design and contains the instantiations of datapath.v and control_unit.v. These two modules further instantiate all the lower-level building blocks like the ALU, register file, memory, multiplexers, etc., to complete the processor architecture.

Tools Used

• Quartus Prime – For writing, compiling, and deploying Verilog code.
• ModelSim – For simulation and debugging.
• DE-1 SoC FPGA Board – As the hardware target platform.

Goal of the Project

The main objective is to understand and implement the internal working of a RISC-V CPU on an FPGA, focusing on datapath design, instruction decoding, and memory access.

Related Work

If you're new to Verilog or want to brush up on the basics, check out this repo: Getting Started with Verilog