add riscv rvv ci

[zijianli1234]

This PR introduces CI testing for RISC-V RVV (Vector Extension) to validate the correctness of the RVV code across various vector lengths: vlen=128, 256, and 512.
Additionally, it addresses a bug related to "cast increases required alignment of target type".

[Cyan4973]

This is indeed an important test to run in CI since RVV extension has been added to XXH3.

[zijianli1234]

hi @Cyan4973, this PR has problems?

[camel-cdr]

I recommend additionally setting the rvv_ta_all_1s=on,rvv_ma_all_1s=on flags, to make sure improper use of the agnostic policy produces errors, and if the qemu version available is new enough rvv_vl_half_avl=on to make sure the permitted vsetvl behavior for AVL<VLMAX*2 && AVL>VLMAX is tested properly.

[zijianli1234]

I recommend additionally setting the rvv_ta_all_1s=on,rvv_ma_all_1s=on flags, to make sure improper use of the agnostic policy produces errors, and if the qemu version available is new enough rvv_vl_half_avl=on to make sure the permitted vsetvl behavior for AVL<VLMAX*2 && AVL>VLMAX is tested properly.

Thanks for your suggestions. rvv_ta_all_1s=on,rvv_ma_all_1s=on has been added to the end of the QEMU launch parameters. However, the current QEMU version is 8.2.2, released in 2023, while rvv_vl_half_avl=on was introduced in August 2024, so it is not added for now.