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╚═════╝ ╚══════╝╚══════╝╚═╝ ╚═╝ ╚═╝╚═╝
A high-performance memristor-based logic synthesis toolchain with advanced scheduling and mapping capabilities.
Delphi is a modern implementation of a memristor-based logic synthesis toolchain, designed for optimizing digital circuits for implementation on memristor crossbar arrays. It converts NOT/NOR netlists into optimized crossbar configurations, providing both naive and compact mapping strategies.
- Rust (1.67.0 or newer) - Install Rust
- Cargo package manager (included with Rust)
# Clone the repository
git clone https://github.com/CynicPixel/delphi.git
cd delphi
# Build in release mode
cargo build --release
# The executable will be available at
# .\target\release\delphi.exe# Clone the repository
git clone https://github.com/CynicPixel/delphi.git
cd delphi
# Build in release mode
cargo build --release
# The executable will be available at
# ./target/release/delphiUSAGE:
delphi [OPTIONS] <COMMAND>
COMMANDS:
process Process a single netlist file
bench Process an entire benchmark suite
benchmark Run performance comparison between sequential and parallel implementations
help Print this message or the help of the given subcommand(s)
OPTIONS:
-h, --help Print help information
-V, --version Print version information
# Basic usage
.\delphi process <NETLIST>
# With options
.\delphi process <NETLIST> --output <DIR> --disable-parallel# Basic usage
./delphi process <NETLIST>
# With options
./delphi process <NETLIST> --output <DIR> --disable-parallel<NETLIST>: Path to the netlist file (required)-o, --output <DIR>: Output directory for results (default: ./Results)--disable-parallel: Disable parallel processing
# Process c17 benchmark with parallel processing
.\delphi process C:\path\to\BENCH\netlist\iscas85_c17.txt
# Process with custom output directory and sequential processing
.\delphi process C:\path\to\BENCH\netlist\iscas85_c17.txt -o .\my_results --disable-parallel# Basic usage
.\delphi.exe bench <DIR>
# With options
.\delphi bench <DIR> --output <OUTPUT_DIR> --pattern <PATTERN> --disable-parallel# Basic usage
./delphi bench <DIR>
# With options
./delphi bench <DIR> --output <OUTPUT_DIR> --pattern <PATTERN> --disable-parallel<DIR>: Path to the benchmark directory (required)-o, --output <DIR>: Output directory for results (default: ./Results)-p, --pattern <PATTERN>: Only process files matching this pattern--disable-parallel: Disable parallel processing
# Process all benchmarks in a directory
.\delphi bench C:\path\to\BENCH\netlist\
# Process only iscas85 benchmarks
.\delphi bench C:\path\to\BENCH\netlist\ -p iscas85# Basic usage
.\delphi benchmark <NETLIST>
# With options
.\delphi benchmark <NETLIST> --iterations <ITERATIONS># Basic usage
./delphi benchmark <NETLIST>
# With options
./delphi benchmark <NETLIST> --iterations <ITERATIONS><NETLIST>: Path to the netlist file (required)-i, --iterations <ITERATIONS>: Number of iterations for accurate timing (default: 3)
# Benchmark c17 with default iterations
.\delphi benchmark C:\path\to\BENCH\netlist\iscas85_c17.txt
# Benchmark with 10 iterations
.\delphi benchmark C:\path\to\BENCH\netlist\iscas85_c17.txt -i 10Delphi generates several output files organized in subdirectories under the specified output directory:
Windows:
Results\
├── magic\
│ └── [benchmark]_magic.v # NOR/NOT mapped Verilog module
├── micro_ins_compact\
│ └── [benchmark]_compact.txt # Compact mapping micro-operations
├── micro_ins_naive\
│ └── [benchmark]_naive.txt # Naive mapping micro-operations
└── schedule_stats\
└── [benchmark]_stats.txt # Scheduling statistics
macOS/Linux:
Results/
├── magic/
│ └── [benchmark]_magic.v # NOR/NOT mapped Verilog module
├── micro_ins_compact/
│ └── [benchmark]_compact.txt # Compact mapping micro-operations
├── micro_ins_naive/
│ └── [benchmark]_naive.txt # Naive mapping micro-operations
└── schedule_stats/
└── [benchmark]_stats.txt # Scheduling statistics
-
Magic Verilog (
_magic.v)- NOR/NOT mapped module definition
- Input, output, and wire declarations
- Gate instantiations
-
Naive Mapping (
_naive.txt)- Micro-operations for naive crossbar mapping
- Simple, linear mapping strategy
- Each level's operations listed separately
-
Compact Mapping (
_compact.txt)- Micro-operations for optimized compact mapping
- Efficiently utilizes crossbar space
- Each level's operations listed separately
-
Schedule Statistics (
_stats.txt)- ASAP, ALAP, and LIST scheduling metrics
- Gate distribution across levels
- Crossbar size and time step information
- Performance comparisons
# View statistics
type Results\schedule_stats\iscas85_c17_stats.txt
# View Verilog mapping
type Results\magic\iscas85_c17_magic.v
# View micro-operations
type Results\micro_ins_naive\iscas85_c17_naive.txtDelphi supports parallel processing to speed up computations for larger circuits:
# Enable parallel processing (default)
.\delphi process <NETLIST>
# Disable parallel processing
.\delphi process <NETLIST> --disable-parallelThe parallel implementation:
- Automatically adjusts to the number of available CPU cores
- Only activates for circuits with 100+ gates
- Provides significant speedup for larger benchmarks
- Falls back to sequential processing for small circuits
You can process specific benchmark types or patterns:
# Process only iscas85 benchmarks
.\delphi bench C:\path\to\benchmarks -p iscas85
# Process only c17 benchmark variants
.\delphi bench C:\path\to\benchmarks -p c17Compare sequential and parallel implementations:
.\delphi benchmark <NETLIST> -i 5This will:
- Run both sequential and parallel versions multiple times
- Measure execution time for each stage
- Calculate speedup metrics
- Display detailed performance comparisons
Path Separators:
Windows uses backslashes (\) in paths, while the command line might require either escaped backslashes (\\) or forward slashes (/).
File Access Permissions: If you encounter permission errors, try running the command prompt or PowerShell as Administrator.
Network Paths:
If your files are on a network drive, use the full UNC path (e.g., \\server\share\path\to\file.txt).
File Not Found:
Error: Failed to parse netlist: No such file or directory
Solution: Check that the netlist file path is correct and accessible.
Invalid Benchmark Directory:
Error: Invalid benchmark directory
Solution: Ensure the benchmark directory exists and contains netlist files.
Parsing Errors:
Error: Failed to parse netlist: Invalid format at line X
Solution: Verify that the netlist file follows the required format for NOT/NOR gates.
# Process a single benchmark
.\delphi process C:\path\to\BENCH\netlist\iscas85_c17.txt
# View the statistics
type Results\schedule_stats\iscas85_c17_stats.txt
# View the Verilog mapping
type Results\magic\iscas85_c17_magic.v# Create output directory
mkdir my_results
# Process all iscas benchmarks
.\delphi bench C:\path\to\BENCH\netlist -p iscas -o my_results# Detailed benchmark with 5 iterations
.\delphi benchmark C:\path\to\BENCH\netlist\iscas85_c7552.txt -i 5Contributions are welcome! Please feel free to submit a Pull Request.
- Fork the repository
- Create your feature branch (
git checkout -b feature/amazing-feature) - Commit your changes (
git commit -m 'Add some amazing feature') - Push to the branch (
git push origin feature/amazing-feature) - Open a Pull Request
This project is licensed under the MIT License - see the LICENSE file for details.
For more information or issues, please open an issue on the GitHub repository.