MIPS Pipelining Matrix multiplicator

This is a verilog code which simulates a computer which can multiply 2 matrices of dimensions 3x3 which uses pipelininng.

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
README.md		README.md
a.out		a.out
alu_IMT2017503.v		alu_IMT2017503.v
alu_control_IMT2017503.v		alu_control_IMT2017503.v
control_IMT2017503.v		control_IMT2017503.v
data_memory_IMT2017503.v		data_memory_IMT2017503.v
ex_mem_pipe_reg_IMT2017503.v		ex_mem_pipe_reg_IMT2017503.v
id_ex_pipe_reg_IMT2017503.v		id_ex_pipe_reg_IMT2017503.v
if_id_pipe_reg_IMT2017503.v		if_id_pipe_reg_IMT2017503.v
instr_mem_file_IMT2017503.v		instr_mem_file_IMT2017503.v
mem_wb_pipe_reg_IMT2017503.v		mem_wb_pipe_reg_IMT2017503.v
mips_IMT2017503.v		mips_IMT2017503.v
mips_tb_IMT2017503.v		mips_tb_IMT2017503.v
mux_5_bit_IMT2017503.v		mux_5_bit_IMT2017503.v
mux_IMT2017503.v		mux_IMT2017503.v
reg_file_IMT2017503.v		reg_file_IMT2017503.v

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