A Eurorack dual VCA based on the AS3330 chip — two independent voltage-controlled amplifiers in one PDIP-18 package, each with simultaneous linear and exponential control inputs. Wide control range (120 dB), low distortion (<0.1%), low feedthrough (<−90 dB).
This design adds a Lin/Exp blend knob per channel (smooth pan between linear and exponential response), a CV attenuator + offset for shaping the control signal, an LED level indicator, and a mix output that sums both VCAs.
- Two independent VCAs in one chip (AS3330 PDIP-18)
- Per-channel Lin/Exp blend — one knob smoothly mixes linear and exponential CV response
- CV attenuator + offset per channel — handles ±5V, 0–5V, or 0–10V CV ranges
- Mix output (Sig 1 + Sig 2 summed via U5A/U5B)
- Output-2 select jumper (JP1) — Sig 2 jack outputs either VCA2 directly or the Mix
- Bipolar LED indicator per channel — shows CV level
- Eurorack ±12V power via either 16-pin IDC or 3-pin JST connector
- Local −5V reference rail (
-5VREF) generated by a TL072-based reference for CV scaling
| Jack | Range | Notes |
|---|---|---|
| Sig In 1 | 10 Vpp (±5V) | Through 100K (Rl) to chip pin 4 IN1 |
| Sig In 2 | 10 Vpp (±5V) | Through 100K (Rl) to chip pin 13 IN2 |
| CV1 In | ±5V / 0–5V / 0–10V | Routed through CV scaling section (atten + offset + Lin/Exp blend) |
| CV2 In | ±5V / 0–5V / 0–10V | Same |
| Sig Out 1 | 10 Vpp (±5V) | Transimpedance buffer with R5 (100K) feedback |
| Sig Out 2 / Mix Out | 10 Vpp | JP1 selects between Sig Out 2 alone or the Mix Out (sum of both VCAs) |
Front-panel pots (per channel):
| Pot | Value | Function |
|---|---|---|
| RV1 / RV4 | 100K | CV Attenuation — scales the CV jack signal |
| RV3 / RV6 | 10K | CV Offset — adds a manual offset (−5V to +5V via −5V_REF) |
| RV2 / RV5 | 10K | Lin/Exp blend — fully left = pure linear response, fully right = pure exponential |
Internal trim:
| Trim | Value | Function |
|---|---|---|
| RV7 | 10K | Sets the −5V_REF level (TL072 reference generator) |
CV in ──[RV1 100K atten]──┐
▼
−5V_REF ──[RV3 10K offset]──┐
▼
[TL074 inverting summer + LED driver]
│
▼
[RV2 10K Lin/Exp blend pot]
├── (left tap) ──► [TL074 inverter + BAT42 clamp] ──► Linear CV (chip pin 7 / 12)
└── (right tap) ──► [TL074 offset + BAT42 clamp] ──► Exponential CV (chip pin 6 / 14)
Sig in ──[Rl 100K]──► AS3330 pin 4 IN1 / pin 13 IN2
AS3330:
Pin 1 / 16 Out1/2 ──► [TL072 transimpedance, RF 100K] ──[1K series]──► Sig Out 1 / 2 jack
Pin 2 / 15 VG1/2 ──[RB 120K to +12V]──► Iref = 100 µA (per datasheet's 100 µA design point)
[also 1nF compensation cap]
Pin 3 / 17 DTrim1/2 ── GND (no distortion trim — see Design notes)
Pin 6 / 14 VCE1/2 ──[Rce 33K + Ri 1K to GND, divider]──► from Exp CV path
Pin 7 / 12 VCL1/2 ──[Rcl 100K]──► from Linear CV path
Pin 8 IDLE ──[Ridle 68K to +12V]── Class A bias
Pin 5 VEE ──[REE 560 Ω]── −12V
Pin 9 / 11 CCOMP1/2 ──[5 nF to GND]── log-converter compensation
Pin 10 VCC ── +12V
Pin 18 GND ── GND
Mix Out: Sig Out 1 ──[R42 100K]──┐
Sig Out 2 ──[R43 100K]──┴── U5A inverting summer ──[U5B unity inverter]── R41 1K ──► Mix Out
(JP1 selects whether J10 = Sig Out 2 direct or Mix Out)
- Eurorack ±12V via J8 (3-pin JST) or J9 (16-pin IDC) — populate one
- D13 / D14: reverse-polarity protection
- C14 / C15 (22 µF): bulk rail decoupling
- C19 / C20 / C21 / C22 / C23 (100 nF) on each op-amp's supply pins
- C16 / C18 (100 nF) decoupling near AS3330 VCC / VEE pins
- R48 = 560 Ω — AS3330 VEE current limiter for −12V supply
REE formula (datasheet uses 680 Ω at ±15V):
| VEE supply | REE | I through REE |
|---|---|---|
| −15V | 680 Ω | ~13 mA (datasheet) |
| −12V | 560 Ω ← used here | ~8.2 mA |
| −5V | none needed | (under threshold) |
Datasheet abs max for current into VEE pin is ±40 mA per pin — both options well within spec.
Local −5V reference (−5V_REF): generated by a TL072 + RV7 (10K) network. This provides the negative half of the CV offset range. Trim RV7 to set −5V exactly (see Calibration).
This module has one internal trim (RV7) plus six front-panel pots per stereo pair (twelve total). Front-panel pots are runtime controls. Only RV7 is a true calibration trim.
RV7 — −5V_REF trim.
- Power up the module and let it warm up 5 minutes.
- Probe the −5VREF test point (TP1) or any other point on the −5V reference net.
- Adjust RV7 until the reading is −5.00 V (or as close as a DMM allows).
Once −5V_REF is calibrated, both channels' CV offset behavior tracks correctly: with RV3/RV6 at minimum, the CV path is offset by −5V; at maximum, +5V; centered, 0V.
If the design adds distortion trim pots on chip pins 3 / 17 in a future revision (see #issues), the calibration procedure would extend with a per-channel distortion null using a 1 kHz reference signal.
This design tunes the AS3330's reference network for ±12V Eurorack supplies rather than the datasheet's ±15V. The scaling preserves the datasheet's intended operating currents:
| Value | Datasheet (±15V) | This design (±12V) | Why |
|---|---|---|---|
| RB (Gain bias) | 150K to +15V → 100 µA | 120K to +12V → 100 µA | Iref preserved for scale accuracy |
| REE (VEE limit) | 680 Ω → ~13 mA | 560 Ω → ~8 mA | Same protection, lower power |
| Rcl (Lin series) | 100K | 100K | Unchanged |
| Rce (Exp series) | 33K + 1K | 33K + 1K | Unchanged |
| Ridle | 6.8K (datasheet example), 68K (Class A) | 68K — Class A | Lower distortion, higher idle power |
| Ccomp | 5 nF | 5 nF | Unchanged |
| RF (transimpedance) | 51K → max gain 0.51× | 100K → max gain ~1× | Match input level on output (10 Vpp in → 10 Vpp out) |
The RF = 100K choice deviates from the datasheet's 51K. Trade-off: for Eurorack ±5V signals, 100K gives unity gain at the output (input level = output level when CV is at max). The datasheet's 51K leaves more headroom — at max gain with full-scale signal, the chip's cell-current gain spec (up to 1.2×) means output could reach ~12V briefly. At ±5V signal levels with 100K, no clipping in practice. Verify with a scope at max gain and full-scale input.
The README cites the Digisound 80-9 VCA3330 as a reference. Side-by-side, the two designs differ in five places worth knowing:
| Choice | This design | Digisound 80-9 | Comment |
|---|---|---|---|
| Distortion trim (pin 3 / 17) | GND | Trim pot via 5K + 100K | Digisound trims for low CV feedthrough; this design accepts untrimmed feedthrough (datasheet spec: ±5 µA in Class A) |
| Signal input AC coupling | DC | 330 nF AC coupling | Digisound is audio-only; this design accepts DC for CV-as-signal use |
| Signal input latch-up diode | None | 1N4148 to clamp | Digisound protects against >±6V transients on signal pin |
| RB (Gain bias) | 120K @ +12V → 100 µA | 100K @ +12V → 120 µA | Both work; this design hits the datasheet's 100 µA target exactly |
| Ridle | 68K (Class A) | 6.8K | Different distortion / power trade-off |
| CV control | Lin/Exp blend knob + offset + atten | Separate jacks for Lin / Exp / AM | Different design intent — performer vs studio |
Local archived copies live in references/ so this repo stays useful if the upstream links die.
- AS3330 datasheet — local copy · upstream (alfatriode.lv)
- Digisound 80-9 VCA3330 schematic — local copy · upstream
- Digisound 80-9 module page (calibration / theory)
- Electric Druid AS3330 product page
- Geofex panner article — useful theory for CV-controlled gain math
- LT AN148 — log/antilog amp app note — chip-internal log converter background
- Design inspiration: Intellijel's Quad VCA module (lin/exp response, CV offset)
What's ready for builders today, and what's still on the TODO list:
Production assets (what you need to actually fabricate and assemble a final unit)
- Schematic — Rev 0.1.7 (AS3330-Dual-Linear-Exponential-VCA-Schematic-Rev0.1.7.pdf)
- PCB layout — in progress — single working layout in
kicad/, not yet separated for fab - Gerber files for fabrication — none yet
- BOM — none yet
- Final front panel (SVG/PDF for fab) — none yet
- License — none yet
Prototype assets (for breadboard / perfboard / 3D-printed-panel builds before final PCB)
- 3D-printed prototype panel STL — 3330_VCA.stl
- Falstad simulations — falstad/
Documentation
- Photos of the assembled module — none yet (drop in
photos/) - Demo video — none yet
- Build / assembly instructions — none yet
- Calibration notes — see Calibration section above
Want to help fill a gap (build photos, gerbers, an assembly guide)? Open an issue or PR.