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FPGA Pins

Håvard O. Nordstrand edited this page Oct 25, 2019 · 3 revisions

A mapping between pin names of fpga and PACKAGE_PIN, which is used in the constraints file to connect fpga pins to chisel i/o variables.

Pin Name PACKAGE_PIN Description
IO_L3P_T0_DQS_PUDC_B_14 L15 SYSCLK ADC/DAC
IO_L3N_T0_DQS_EMCCLK_14 M15 LRCLK ADC/DAC
IO_L4P_T0_D04_14 L14 BITCLK ADC/DAC
IO_L4N_T0_D05_14 M14 FPGAIn ADC/DAC
IO_L5P_T0_D06_14 K13 FPGAOut ADC/DAC
IO_L6N_T0_D08_VREF_14 M12 GPIO_3 MCU
IO_L7P_T1_D09_14 M16 GPIO_2 MCU
IO_L7N_T1_D10_14 N16 GPIO_1 MCU
IO_L8P_T1_D11_14 P15 GPIO_0 MCU
IO_L8N_T1_D12_14 P16 SS MCU
IO_L9P_T1_DQS_14 R15 MISO MCU
IO_L9N_T1_DQS_D13_14 R16 MOSI MCU
IO_L10P_T1_D14_14 T14 SCLK MCU
IO_L12P_T1_MRCC_14 N14 16MHz Oscillator
IO_L12N_T1_MRCC_14 P14 FPGA_pinout_1
IO_L13P_T2_MRCC_14 N11 FPGA_pinout_2
IO_L13N_T2_MRCC_14 N12 FPGA_pinout_3
IO_L14P_T2_SRCC_14 P10 FPGA_pinout_4
IO_L14N_T2_SRCC_14 P11 FPGA_pinout_5
IO_L15P_T2_DQS_RDWR_B_14 R12 FPGA_pinout_6
IO_L15N_T2_DQS_DOUT_CSO_B_14 T12 FPGA_pinout_7
IO_L16P_T2_CSI_B_14 R13 FPGA_pinout_8
IO_L16N_T2_A15_D31_14 T13 FPGA_pinout_9
IO_L17P_T2_A14_D30_14 R10 FPGA_pinout_10
IO_L17N_T2_A13_D29_14 R11 FPGA_pinout_11
IO_L18P_T2_A12_D28_14 N9 FPGA_pinout_12
IO_L18N_T2_A11_D27_14 P9 FPGA_pinout_13
IO_L19P_T3_A10_D26_14 M6 FPGA_pinout_14
IO_L19N_T3_A09_D25_VREF_14 N6 FPGA_pinout_15
IO_L20P_T3_A08_D24_14 P8 FPGA_pinout_16

Full table for XC7A100T FTG256

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