add tcgen.ld.red support to sm103a arch#2696
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stack-info: PR: #2696, branch: drisspg/stack/47
stack-info: PR: #2696, branch: drisspg/stack/47
stack-info: PR: #2696, branch: drisspg/stack/47
stack-info: PR: #2696, branch: drisspg/stack/47
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| if const_expr(self.use_ldred_rowmax): | ||
| # ld.red returns each x32 tile's max in an extra register. | ||
| tSrS_red = cute.make_rmem_tensor(((1, 1), *tSrS_t2r.shape[1:]), self.qk_acc_dtype) | ||
| cute.copy(thr_tmem_load, tStS_t2r, (tSrS_t2r, tSrS_red)) |
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Prevent ld.red loads from being optimized across tiles
On SM103 dense kernels with more than one K tile, this ld.red load reads the same tStS_t2r TMEM address on each softmax_step while intervening MMA operations overwrite that slot. CUTLASS has lowered LdRed through side-effect-free inline asm unlike regular Ld32, so repeated reads from the same TMEM address can be CSE'd or hoisted and later tiles can reuse stale scores/max values, corrupting attention results. Please keep the normal TMEM load or use a side-effecting/fenced ld.red wrapper before enabling this path.
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stack-info: PR: #2696, branch: drisspg/stack/47
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Reviewed commit: 1a9f9ebf86
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ad tcgen.ld.red support to sm103a arch
Inspired by; https://github.com/hao-ai-lab/flash-attention-fp4
Perf on dense non casual; makes sense msotly i dont really know why headim32 takes a hit though -> ill just update the expr to not dispatch for this
causal is similar