MTL TCSS fixes

src/mainboard/novacustom/mtl-h/acpi/mainboard.asl

@@ -7,6 +7,7 @@
 #include <ec/dasharo/ec/acpi/ec.asl>
 
 Scope (\_SB) {
+	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
 	}

src/mainboard/novacustom/mtl-h/acpi/sleep.asl

@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/gpio.h>
+
+Method (PGPM, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < 6, Local0++)
+	{
+		\_SB.PCI0.CGPM (Local0, Arg0)
+	}
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+	PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
+
+#if CONFIG(D3COLD_SUPPORT)
+	/* Bring system out of TC cold before enter Sx */
+	\_SB.PCI0.TCON ()
+
+	/* Bring TBT group 0 and 1 out of D3 cold if it is in D3 cold */
+	\_SB.PCI0.TG0N ()
+	\_SB.PCI0.TG1N ()
+#endif
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+	PGPM (0)
+
+	If (CondRefOf (\_SB.PCI0.TXHC)) {
+		\_SB.TCWK (Arg0)
+	}
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.PEPD._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+	If (Arg0 == 1) {
+		/* S0ix Entry */
+		PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
+	} Else {
+		/* S0ix Exit */
+		PGPM (0)
+#if CONFIG(D3COLD_SUPPORT)
+		/* Bring system out of TC cold  */
+		\_SB.PCI0.TCON ()
+
+		/* Bring TBT group 0 and 1 out of D3 cold if it is in D3 cold */
+		\_SB.PCI0.TG0N ()
+		\_SB.PCI0.TG1N ()
+#endif
+	}
+}
+
+/*
+ * Display Notifications
+ * Called from \_SB.PEPD._DSM
+ */
+Method (MSDX, 1, Serialized)
+{
+	If (CondRefOf (\_SB.PCI0.IMNG))
+	{
+		\_SB.PCI0.IMNG (Arg0)
+	}
+}

src/mainboard/novacustom/mtl-h/devicetree.cb

@@ -75,7 +75,7 @@ chip soc/intel/meteorlake
 			# Bit0,Bit2,Bit4,Bit6 set to "1" indicates no retimer on USBC Ports
 			# Bit1,Bit3,Bit5,Bit7 set to "0" indicates Aux lines are not swapped on the
 			# motherboard to USBC connector
-			register "tcss_aux_ori" = "0x54"
+			register "tcss_aux_ori" = "0x00"
 
 			register "tcss_ports" = "{
 				[0] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 1 (TBT) */
@@ -89,13 +89,15 @@ chip soc/intel/meteorlake
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
 						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))"
+						register "usb_lpm_incapable" = "true"
 						device ref tcss_usb3_port0 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port 2""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
 						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
+						register "usb_lpm_incapable" = "true"
 						device ref tcss_usb3_port1 on end
 					end
 				end
@@ -110,10 +112,12 @@ chip soc/intel/meteorlake
 		end
 		device ref ioe_shared_sram on end
 		device ref xhci on
+			register "usb2_wake_enable_bitmap" = "0x27"
+			register "usb3_wake_enable_bitmap" = "0x3"
 
 			register "usb2_ports" = "{
 				[0] = USB2_PORT_LONG(OC_SKIP),	 /* USB Type-A Port 1 (Left) */
-				[1] = USB2_PORT_MID(OC_SKIP),	 /* USB Type-C Port 1 (Non-TBT) */
+				[1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 1 (Non-TBT) */
 				[2] = USB2_PORT_MID(OC_SKIP),	 /* USB Type-A Port 2 (Right) */
 				[5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 2 (TBT) */
 				[6] = USB2_PORT_LONG(OC_SKIP),	 /* Integrated Camera */

src/mainboard/novacustom/mtl-h/ramstage.c

@@ -5,6 +5,7 @@
 #include <ec/acpi/ec.h>
 #include <ec/dasharo/ec/acpi.h>
 #include <fmap.h>
+#include <gpio.h>
 #include <lib.h>
 #include <mainboard/variants.h>
 #include <security/vboot/vboot_common.h>
@@ -235,6 +236,12 @@ void __weak variant_final(void)
 static void mainboard_final(void *chip_info)
 {
 	variant_final();
+
+	/*
+	 * De-assert TBT force power to allow RTD3.
+	 * It is asserted by default in gpio tables.
+	 */
+	gpio_set(GPP_B21, 0);
 }
 
 struct chip_operations mainboard_ops = {
@@ -261,7 +268,13 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->CnviRfResetPinMux = 0x194CE404; // GPP_F4
 	params->CnviClkreqPinMux = 0x394CE605;  // GPP_F5
 
-	params->EnableTcssCovTypeA[1] = 1;
+	/*
+	 * [3:0] MappingPchXhciUsbA (1-based USB2 port numbering)
+	 * [5:4] Reserved
+	 * [6]   Orientation - TCSS port uses TX0/RX0 pairs or TX1/RX1 pairs
+	 * [7]   Enable
+	 */
+	params->EnableTcssCovTypeA[1] = 0x82;
 
 	/* Disable S0i2.x due to wake issues */
 	params->PmcLpmS0ixSubStateEnableMask = BIT(0);
@@ -270,4 +283,9 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 
 	params->PortResetMessageEnable[1] = 1;
 	params->PortResetMessageEnable[5] = 1;
+
+	params->PmcPdEnable = 1;
+	params->TcCstateLimit = 10;
+	params->TcNotifyIgd = 1;
+	params->PsOnEnable = 0;
 }

src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c

@@ -234,7 +234,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_B18, 1, DEEP),	/* GPIO - PCH_BT_EN */
 	PAD_CFG_GPO(GPP_B19, 1, DEEP),	/* GPIO - WIFI_RF_EN */
 	PAD_CFG_GPO(GPP_B20, 0, DEEP),	/* GPIO */
-	PAD_CFG_GPO(GPP_B21, 0, PLTRST),	/* GPIO - TBT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_B21, 1, PLTRST),	/* GPIO - TBT_FORCE_PWR */
 	PAD_CFG_GPO(GPP_B22, 0, DEEP),	/* GPIO */
 	PAD_CFG_TERM_GPO(GPP_B23, 0, DN_20K, DEEP),	/* GPIO */
 	PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4),	/* n/a */

src/soc/intel/alderlake/fsp_params.c

@@ -1417,7 +1417,7 @@ static void wait_for_panel_power_cycle_done(const struct soc_intel_alderlake_con
 	if (!CONFIG(RUN_FSP_GOP))
 		return;
 
-	bar0 = pci_s_read_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0);
+	bar0 = pci_read_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0);
 	mmio = (void *)(bar0 & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
 	if (!mmio)
 		return;

src/soc/intel/alderlake/include/soc/pci_devs.h

@@ -5,81 +5,81 @@
 
 #include <device/pci_def.h>
 
-#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
+#define _SA_DEVFN(slot, func)	PCI_DEVFN(SA_DEV_SLOT_ ## slot, func)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#define _SA_DEV(slot)		pcidev_path_on_root(_SA_DEVFN(slot))
+#define _SA_DEV(slot, func)	pcidev_path_on_root(_SA_DEVFN(slot, func))
 #define _PCH_DEV(slot, func)	pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
 #else
-#define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
+#define _SA_DEV(slot, func)	PCI_DEV(0, SA_DEV_SLOT_ ## slot, func)
 #define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
 #endif
 
 /* System Agent Devices */
 
 #define SA_DEV_SLOT_ROOT	0x00
-#define  SA_DEVFN_ROOT		PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)
+#define  SA_DEVFN_ROOT		_SA_DEVFN(ROOT, 0)
 #if defined(__SIMPLE_DEVICE__)
-#define  SA_DEV_ROOT		PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
+#define  SA_DEV_ROOT		_SA_DEV(ROOT, 0)
 #endif
 
 #define SA_DEV_SLOT_CPU_1	0x01
-#define  SA_DEVFN_CPU_PCIE1_0	PCI_DEVFN(SA_DEV_SLOT_CPU_1, 0)
-#define  SA_DEVFN_CPU_PCIE1_1	PCI_DEVFN(SA_DEV_SLOT_CPU_1, 1)
+#define  SA_DEVFN_CPU_PCIE1_0	_SA_DEVFN(CPU_1, 0)
+#define  SA_DEVFN_CPU_PCIE1_1	_SA_DEVFN(CPU_1, 1)
 
 #define SA_DEV_SLOT_IGD		0x02
-#define  SA_DEVFN_IGD		PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
-#define  SA_DEV_IGD		PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
+#define  SA_DEVFN_IGD		_SA_DEVFN(IGD, 0)
+#define  SA_DEV_IGD		_SA_DEV(IGD, 0)
 
 #define SA_DEV_SLOT_DPTF	0x04
-#define  SA_DEVFN_DPTF		PCI_DEVFN(SA_DEV_SLOT_DPTF, 0)
-#define  SA_DEV_DPTF		PCI_DEV(0, SA_DEV_SLOT_DPTF, 0)
+#define  SA_DEVFN_DPTF		_SA_DEVFN(DPTF, 0)
+#define  SA_DEV_DPTF		_SA_DEV(DPTF, 0)
 
 #define SA_DEV_SLOT_IPU		0x05
-#define  SA_DEVFN_IPU		PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
-#define  SA_DEV_IPU		PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
+#define  SA_DEVFN_IPU		_SA_DEVFN(IPU, 0)
+#define  SA_DEV_IPU		_SA_DEV(IPU, 0)
 
 #define SA_DEV_SLOT_CPU_6	0x06
-#define  SA_DEVFN_CPU_PCIE6_0	PCI_DEVFN(SA_DEV_SLOT_CPU_6, 0)
-#define  SA_DEVFN_CPU_PCIE6_2	PCI_DEVFN(SA_DEV_SLOT_CPU_6, 2)
+#define  SA_DEVFN_CPU_PCIE6_0	_SA_DEVFN(CPU_6, 0)
+#define  SA_DEVFN_CPU_PCIE6_2	_SA_DEVFN(CPU_6, 2)
 
 #define SA_DEV_SLOT_TBT		0x07
-#define SA_DEVFN_TBT(x)		PCI_DEVFN(SA_DEV_SLOT_TBT, (x))
+#define SA_DEVFN_TBT(x)		_SA_DEVFN(TBT, (x))
 #define NUM_TBT_FUNCTIONS	4
-#define  SA_DEVFN_TBT0		PCI_DEVFN(SA_DEV_SLOT_TBT, 0)
-#define  SA_DEVFN_TBT1		PCI_DEVFN(SA_DEV_SLOT_TBT, 1)
-#define  SA_DEVFN_TBT2		PCI_DEVFN(SA_DEV_SLOT_TBT, 2)
-#define  SA_DEVFN_TBT3		PCI_DEVFN(SA_DEV_SLOT_TBT, 3)
-#define  SA_DEV_TBT0		PCI_DEV(0, SA_DEV_SLOT_TBT, 0)
-#define  SA_DEV_TBT1		PCI_DEV(0, SA_DEV_SLOT_TBT, 1)
-#define  SA_DEV_TBT2		PCI_DEV(0, SA_DEV_SLOT_TBT, 2)
-#define  SA_DEV_TBT3		PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
+#define  SA_DEVFN_TBT0		_SA_DEVFN(TBT, 0)
+#define  SA_DEVFN_TBT1		_SA_DEVFN(TBT, 1)
+#define  SA_DEVFN_TBT2		_SA_DEVFN(TBT, 2)
+#define  SA_DEVFN_TBT3		_SA_DEVFN(TBT, 3)
+#define  SA_DEV_TBT0		_SA_DEV(TBT, 0)
+#define  SA_DEV_TBT1		_SA_DEV(TBT, 1)
+#define  SA_DEV_TBT2		_SA_DEV(TBT, 2)
+#define  SA_DEV_TBT3		_SA_DEV(TBT, 3)
 
 #define SA_DEV_SLOT_GNA		0x08
-#define  SA_DEVFN_GNA		PCI_DEVFN(SA_DEV_SLOT_GNA, 0)
-#define  SA_DEV_GNA		PCI_DEV(0, SA_DEV_SLOT_GNA, 0)
+#define  SA_DEVFN_GNA		_SA_DEVFN(GNA, 0)
+#define  SA_DEV_GNA		_SA_DEV(GNA, 0)
 
 #define SA_DEV_SLOT_TMT		0x0A
-#define SA_DEVFN_TMT		_SA_DEVFN(TMT)
-#define SA_DEV_TMT		_SA_DEV(TMT)
+#define SA_DEVFN_TMT		_SA_DEVFN(TMT, 0)
+#define SA_DEV_TMT		_SA_DEV(TMT, 0)
 
 #define SA_DEV_SLOT_TCSS	0x0d
 #define NUM_TCSS_DMA_FUNCTIONS	2
-#define SA_DEVFN_TCSS_DMA(x)	PCI_DEVFN(SA_DEV_SLOT_TCSS, ((x) + 2))
-#define  SA_DEVFN_TCSS_XHCI	PCI_DEVFN(SA_DEV_SLOT_TCSS, 0)
-#define  SA_DEVFN_TCSS_XDCI	PCI_DEVFN(SA_DEV_SLOT_TCSS, 1)
-#define  SA_DEVFN_TCSS_DMA0	PCI_DEVFN(SA_DEV_SLOT_TCSS, 2)
-#define  SA_DEVFN_TCSS_DMA1	PCI_DEVFN(SA_DEV_SLOT_TCSS, 3)
-#define  SA_DEV_TCSS_XHCI	PCI_DEV(0, SA_DEV_SLOT_TCSS, 0)
-#define  SA_DEV_TCSS_XDCI	PCI_DEV(0, SA_DEV_SLOT_TCSS, 1)
-#define  SA_DEV_TCSS_DMA0	PCI_DEV(0, SA_DEV_SLOT_TCSS, 2)
-#define  SA_DEV_TCSS_DMA1	PCI_DEV(0, SA_DEV_SLOT_TCSS, 3)
+#define SA_DEVFN_TCSS_DMA(x)	_SA_DEVFN(TCSS, ((x) + 2))
+#define  SA_DEVFN_TCSS_XHCI	_SA_DEVFN(TCSS, 0)
+#define  SA_DEVFN_TCSS_XDCI	_SA_DEVFN(TCSS, 1)
+#define  SA_DEVFN_TCSS_DMA0	_SA_DEVFN(TCSS, 2)
+#define  SA_DEVFN_TCSS_DMA1	_SA_DEVFN(TCSS, 3)
+#define  SA_DEV_TCSS_XHCI	_SA_DEV(TCSS, 0)
+#define  SA_DEV_TCSS_XDCI	_SA_DEV(TCSS, 1)
+#define  SA_DEV_TCSS_DMA0	_SA_DEV(TCSS, 2)
+#define  SA_DEV_TCSS_DMA1	_SA_DEV(TCSS, 3)
 
 #define SA_DEV_SLOT_VMD		0x0e
-#define  SA_DEVFN_VMD		PCI_DEVFN(SA_DEV_SLOT_VMD, 0)
-#define  SA_DEV_VMD		PCI_DEV(0, SA_DEV_SLOT_VMD, 0)
+#define  SA_DEVFN_VMD		_SA_DEVFN(VMD, 0)
+#define  SA_DEV_VMD		_SA_DEV(VMD, 0)
 
 /* PCH Devices */
 #define MIN_PCH_SLOT		PCH_DEV_SLOT_SIO0

src/soc/intel/common/block/usb4/usb4.c

@@ -10,6 +10,7 @@
 
 #define INTEL_TBT_IMR_VALID_UUID	"C44D002F-69F9-4E7D-A904-A7BAABDF43F7"
 #define INTEL_TBT_WAKE_SUPPORTED_UUID	"6C501103-C189-4296-BA72-9BF5A26EBE5D"
+#define INTEL_TBT_PCIE_SUPPORTED_UUID	"197DB5E0-F095-4F33-B915-71DD70833E55"
 
 #if CONFIG(HAVE_ACPI_TABLES)
 static const char *tbt_dma_acpi_name(const struct device *dev)
@@ -24,6 +25,51 @@ static const char *tbt_dma_acpi_name(const struct device *dev)
 	}
 }
 
+static bool tbt_pcie_enabled(struct device *tbt_pcie)
+{
+	return (tbt_pcie && tbt_pcie->enabled);
+}
+
+static void tbt_pcie_ports_present(void *arg)
+{
+	uint8_t tbt0_bitmask, tbt1_bitmask;
+
+	tbt0_bitmask = tbt_pcie_enabled(SA_DEV_TBT0) | (tbt_pcie_enabled(SA_DEV_TBT1) << 1);
+	tbt1_bitmask = tbt_pcie_enabled(SA_DEV_TBT2) | (tbt_pcie_enabled(SA_DEV_TBT3) << 1);
+
+	/* Name (PCPN, Buffer (1) {0}) */
+	acpigen_write_name("PCPN");
+	acpigen_emit_byte(BUFFER_OP);
+	acpigen_write_len_f();
+	acpigen_emit_byte(1);
+	acpigen_emit_byte(0);
+	acpigen_pop_len();
+
+	/* If DUID == 1 set TBT0/TBT1 bitmask, else set TBT2/TBT3 bitmask */
+	acpigen_write_if_lequal_namestr_int("DUID", 0);
+	acpigen_write_store_int_to_namestr(tbt0_bitmask, "PCPN");
+	acpigen_write_else();
+	acpigen_write_store_int_to_namestr(tbt1_bitmask, "PCPN");
+	acpigen_write_if_end();
+
+	acpigen_write_return_namestr("PCPN");
+}
+
+static void tbt_dma_caps_info(void *arg)
+{
+	/*
+	 * Bit0 is IMR_VALID, bit1 is WAKE_SUPPORTED, bit2 is vPro Dock supported.
+	 * We hardcode both IMR_VALID and WAKE_SUPPORTED to 1.
+	 */
+	acpigen_write_return_singleton_buffer(3);
+}
+
+static void (*tbt_pcie_helpers[])(void *) = {
+	NULL,					/* enumerate functions (autogenerated) */
+	tbt_pcie_ports_present,			/* Return supported TBT PCIe */
+	tbt_dma_caps_info,			/* Return supported TBT DMA capabilities */
+};
+
 static void tbt_dma_fill_ssdt(const struct device *dev)
 {
 	struct acpi_dp *dsd, *pkg;
@@ -47,6 +93,11 @@ static void tbt_dma_fill_ssdt(const struct device *dev)
 	acpi_dp_add_package(dsd, pkg);
 	acpi_dp_write(dsd);
 
+	acpigen_write_dsm(INTEL_TBT_PCIE_SUPPORTED_UUID,
+			  tbt_pcie_helpers,
+			  ARRAY_SIZE(tbt_pcie_helpers),
+			  NULL);
+
 	acpigen_pop_len(); /* Scope */
 }
 #endif