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File Crash With Verilator/Clang

Status: Open.

#28 In David-Durst/aetherling;

· David-Durst opened on Nov 20, 2019

1D Stencil Is Very Slow

Status: Open.

#25 In David-Durst/aetherling;

· David-Durst opened on Oct 6, 2019

CoreIR Won't Compile Circuit That Simulates Correctly

Status: Open.

#24 In David-Durst/aetherling;

· David-Durst opened on Sep 22, 2019

Can't Access ROM From CoreIR Through Magma

Status: Open.

#23 In David-Durst/aetherling;

· David-Durst opened on Sep 6, 2019

Possible Aetherling/CoreIR Memory Leak

Status: Open.

#19 In David-Durst/aetherling;

· David-Durst opened on May 16, 2019

Port Direction Issue

Status: Open.

#3 In David-Durst/aetherling;

· David-Durst opened on May 20, 2018