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board naming convention should not use dashes

Status: Open.

#49 In Digilent/vivado-boards;

· tempest766 opened on Jan 16, 2025

system clock of IP design is not working on the vivado 2024.1

Status: Open.

#46 In Digilent/vivado-boards;

· eeric9655 opened on Nov 5, 2024

Not able to Add Kintex-7 FPGA (XC7K325T-2FFG900C) board files in the Vivado 2022.1 version

Status: Open.

#45 In Digilent/vivado-boards;

· Damodartampula opened on Mar 9, 2024

Vivado-board tab missing in Vivado 2023.1

Status: Open.

#43 In Digilent/vivado-boards;

· jkmchow opened on Jun 19, 2023

USING FPGA

Status: Open.

#41 In Digilent/vivado-boards;

· K4RAS opened on May 29, 2023

Error while C synthesis on Vitis HLS 2020.1 for Arty A7-35T

Status: Open.

#39 In Digilent/vivado-boards;

· SuperChamp234 opened on Feb 9, 2023

Zedboard MDIO on EMIO

Status: Open.

#38 In Digilent/vivado-boards;

· johnmmower opened on Feb 8, 2023

Arty Z7 Part0_Pins Wrong

Status: Open.

#32 In Digilent/vivado-boards;

· bsparkm opened on Mar 1, 2021

SPI Slave mode SS pin not connected right

Status: Open.

#29 In Digilent/vivado-boards;

· RupertAmann opened on Sep 26, 2020

Support request for DSDB

Status: Open.

#23 In Digilent/vivado-boards;

· wbmrcb opened on Dec 11, 2019

missing board files for Arty S7-50 revision E

Status: Open.

#21 In Digilent/vivado-boards;

· distractedlambda opened on Jul 20, 2019

NetFPGA-1G-CML

Status: Open.

#13 In Digilent/vivado-boards;

· bkzshabbaz opened on Jun 26, 2018