GitHub - DragonAura/MIPS_Pipeline: 2023 夏季学期《数字逻辑与处理器基础实验》课程大作业 · GitHub

Name		Name	Last commit message	Last commit date
report		report
ALU.v		ALU.v
ALUControl.v		ALUControl.v
CPU.v		CPU.v
Control.v		Control.v
DataMemory.v		DataMemory.v
ForwardUnit.v		ForwardUnit.v
Hazard.v		Hazard.v
InstructionMemory.v		InstructionMemory.v
LED.v		LED.v
RegBetween.v		RegBetween.v
RegisterFile.v		RegisterFile.v
UART.v		UART.v
code.asm		code.asm
generate_test_case.cc		generate_test_case.cc
instruction_convert.py		instruction_convert.py
testCPU.v		testCPU.v
top.v		top.v
top.xdc		top.xdc
uart_generate.py		uart_generate.py
uart_rx.v		uart_rx.v
uart_tx.v		uart_tx.v

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2023 夏季学期《数字逻辑与处理器基础实验》课程大作业

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