Skip to content

Bugfix/tb timing compute check #9

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
nicolecathm wants to merge 2 commits into
base: master
Choose a base branch
from
Open

Bugfix/tb timing compute check #9

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
00229ef
add bugfix for compute time vs correctness check
nicolecathm Nov 30, 2023
23d5687
add compute/timing check to last two tbs
nicolecathm Dec 3, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
13 changes: 13 additions & 0 deletions verilog/vtests/accel_dot/accel_dot_tb.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -49,6 +49,8 @@ module accel_dot_tb();
bit [31:0] fp_hex;
//used to access the FP Solutions table
bit [31:0] sol_hex;

reg COMPUTE_FIN;

accel_dot DUT (
.clk,
Expand Down Expand Up @@ -155,6 +157,9 @@ module accel_dot_tb();
endtask

task compute();

COMPUTE_FIN = 'h0;

$display("Sending Input Vector");
for (i = 0; i < 3; ++i) begin
inputs_table_lookup(i, fp_hex);
Expand All @@ -181,15 +186,19 @@ module accel_dot_tb();
assert( (mismatch > -0.000001) && (mismatch < +0.000001) ) else
$fatal(1, "Bad Test Response %h (%f), Expected %h (%f) mismatch:%f",
fp_hex, $bitstoshortreal(fp_hex), sol_hex, $bitstoshortreal(sol_hex), mismatch);


end
$display( "Compute done, finish timing" );
COMPUTE_FIN = 'h1;
endtask

task timeit (
output int cycles
);

cycles = 0;

while ( ! (
(OUTPUT_AXIS_TREADY === 'h1) &&
(OUTPUT_AXIS_TVALID === 'h1) &&
Expand All @@ -201,6 +210,10 @@ module accel_dot_tb();
assert (cycles < 4410) else
$fatal(1, "Running too long, check OUTPUT_AXIS?");
end

@(posedge clk);
assert(COMPUTE_FIN == 'h1) else
$fatal(1, "Timing done before correctness check");

endtask

Expand Down
11 changes: 11 additions & 0 deletions verilog/vtests/accel_dot_20_10/accel_dot_20_10_tb.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -146,6 +146,8 @@ module accel_dot_20_10_tb();
//used to access the FP Solutions table
bit [31:0] sol_hex;

reg COMPUTE_FIN;

accel_dot #(
.ROWS(ROWS),
.COLS(COLS)
Expand Down Expand Up @@ -263,6 +265,9 @@ module accel_dot_20_10_tb();
endtask

task compute();

COMPUTE_FIN = 'h0;

$display("Sending Input Vector");
for (i = 0; i < ROWS; ++i) begin
inputs_table_lookup(i, fp_hex);
Expand Down Expand Up @@ -294,6 +299,8 @@ module accel_dot_20_10_tb();
repeat(2) @(negedge clk);

end
$display( "Compute done, finish timing" );
COMPUTE_FIN = 'h1;
endtask

task timeit (
Expand All @@ -313,6 +320,10 @@ module accel_dot_20_10_tb();
$fatal(1, "Running too long, check OUTPUT_AXIS?");
end

@(posedge clk);
assert(COMPUTE_FIN == 'h1) else
$fatal(1, "Timing done before correctness check");

endtask


Expand Down
11 changes: 11 additions & 0 deletions verilog/vtests/dot/dot_tb.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,8 @@ module dot_tb();
//used to access the FP Solutions table
bit [31:0] sol_hex;

reg COMPUTE_FIN;

dot DUT (
.clk,
.rst,
Expand Down Expand Up @@ -155,6 +157,9 @@ module dot_tb();
endtask

task compute();

COMPUTE_FIN = 'h0;

$display("Sending Input Vector");
for (i = 0; i < 3; ++i) begin
inputs_table_lookup(i, fp_hex);
Expand Down Expand Up @@ -183,6 +188,8 @@ module dot_tb();
fp_hex, $bitstoshortreal(fp_hex), sol_hex, $bitstoshortreal(sol_hex), mismatch);

end
$display( "Compute done, finish timing" );
COMPUTE_FIN = 'h1;
endtask

task timeit (
Expand All @@ -202,6 +209,10 @@ module dot_tb();
$fatal(1, "Running too long, check OUTPUT_AXIS?");
end

@(posedge clk);
assert(COMPUTE_FIN == 'h1) else
$fatal(1, "Timing done before correctness check");

endtask


Expand Down
13 changes: 12 additions & 1 deletion verilog/vtests/dot_20_10/dot_20_10_tb.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,8 @@ module dot_20_10_tb();
bit [31:0] fp_hex;
//used to access the FP Solutions table
bit [31:0] sol_hex;

reg COMPUTE_FIN;

axis_dot_20_10 DUT (
.aclk(clk),
Expand Down Expand Up @@ -152,6 +154,9 @@ module dot_20_10_tb();
endtask

task compute();

COMPUTE_FIN = 'h0;

$display("Sending Input Vector");
for (i = 0; i < 20; ++i) begin
inputs_table_lookup(i, fp_hex);
Expand Down Expand Up @@ -179,6 +184,8 @@ module dot_20_10_tb();
fp_hex, $bitstoshortreal(fp_hex), sol_hex, $bitstoshortreal(sol_hex), error);

end
$display( "Compute done, finish timing" );
COMPUTE_FIN = 'h1;
endtask

task timeit (
Expand All @@ -197,7 +204,11 @@ module dot_20_10_tb();
assert (cycles < 44100) else
$fatal(1, "Running too long, check OUTPUT_AXIS?");
end


@(posedge clk);
assert(COMPUTE_FIN == 'h1) else
$fatal(1, "Timing done before correctness check");

endtask


Expand Down
13 changes: 12 additions & 1 deletion verilog/vtests/dot_40_20/dot_40_20_tb.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,8 @@ module dot_40_20_tb();
bit [31:0] fp_hex;
//used to access the FP Solutions table
bit [31:0] sol_hex;

reg COMPUTE_FIN;

axis_dot_40_20 DUT (
.aclk(clk),
Expand Down Expand Up @@ -163,6 +165,9 @@ module dot_40_20_tb();
endtask

task compute();

COMPUTE_FIN = 'h0;

$display("Sending Input Vector");
for (i = 0; i < ROWS ; ++i) begin
inputs_table_lookup(i, fp_hex);
Expand Down Expand Up @@ -191,6 +196,8 @@ module dot_40_20_tb();
fp_hex, $bitstoshortreal(fp_hex), sol_hex, $bitstoshortreal(sol_hex), mismatch);

end
$display( "Compute done, finish timing" );
COMPUTE_FIN = 'h1;
endtask

task timeit (
Expand All @@ -209,7 +216,11 @@ module dot_40_20_tb();
assert (cycles < 44100) else
$fatal(1, "Running too long, check OUTPUT_AXIS?");
end


@(posedge clk);
assert(COMPUTE_FIN == 'h1) else
$fatal(1, "Timing done before correctness check");

endtask


Expand Down
13 changes: 12 additions & 1 deletion verilog/vtests/dot_80_40/dot_80_40_tb.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,8 @@ module dot_80_40_tb();
bit [31:0] fp_hex;
//used to access the FP Solutions table
bit [31:0] sol_hex;

reg COMPUTE_FIN;

axis_dot_80_40 DUT (
.aclk(clk),
Expand Down Expand Up @@ -181,6 +183,9 @@ module dot_80_40_tb();
endtask

task compute();

COMPUTE_FIN = 'h0;

$display("Sending Input Vector");
for (i = 0; i < ROWS ; ++i) begin
inputs_table_lookup(i, fp_hex);
Expand Down Expand Up @@ -209,6 +214,8 @@ module dot_80_40_tb();
fp_hex, $bitstoshortreal(fp_hex), sol_hex, $bitstoshortreal(sol_hex), mismatch);

end
$display( "Compute done, finish timing" );
COMPUTE_FIN = 'h1;
endtask

task timeit (
Expand All @@ -227,7 +234,11 @@ module dot_80_40_tb();
assert (cycles < 44100) else
$fatal(1, "Running too long, check OUTPUT_AXIS?");
end


@(posedge clk);
assert(COMPUTE_FIN == 'h1) else
$fatal(1, "Timing done before correctness check");

endtask


Expand Down