Add RISC-V vector spec v1.0 support

Makefile.am

@@ -104,6 +104,17 @@ GENERIC_SIMD256_LIBS = dft/simd/generic-simd256/libdft_generic_simd256_codelets.
 rdft/simd/generic-simd256/librdft_generic_simd256_codelets.la
 endif
 
+if HAVE_RVV
+RVV_LIBS = dft/simd/rvv128/libdft_rvv128_codelets.la      \
+rdft/simd/rvv128/librdft_rvv128_codelets.la	\
+dft/simd/rvv256/libdft_rvv256_codelets.la      \
+rdft/simd/rvv256/librdft_rvv256_codelets.la	\
+dft/simd/rvv512/libdft_rvv512_codelets.la      \
+rdft/simd/rvv512/librdft_rvv512_codelets.la	\
+dft/simd/rvv1024/libdft_rvv1024_codelets.la      \
+rdft/simd/rvv1024/librdft_rvv1024_codelets.la
+endif
+
 if THREADS
 if COMBINED_THREADS
 COMBINED_THREADLIBS=threads/libfftw3@PREC_SUFFIX@_threads.la
@@ -127,7 +138,7 @@ libfftw3@PREC_SUFFIX@_la_LIBADD =			\
         $(SIMD_LIBS) $(SSE2_LIBS) $(AVX_LIBS) $(AVX_128_FMA_LIBS) \
         $(AVX2_LIBS) $(ALTIVEC_LIBS) \
         $(VSX_LIBS) $(NEON_LIBS) $(KCVI_LIBS) $(AVX512_LIBS) \
-        $(GENERIC_SIMD128_LIBS) $(GENERIC_SIMD256_LIBS) \
+        $(GENERIC_SIMD128_LIBS) $(GENERIC_SIMD256_LIBS) $(RVV_LIBS) \
 	$(COMBINED_THREADLIBS)
 
 if QUAD

api/version.c

@@ -85,4 +85,8 @@ const char X(version)[] = PACKAGE "-" PACKAGE_VERSION
    "-generic_simd256"
 #endif
 
+#if defined(HAVE_R5V)
+   "-rvv"
+#endif
+
 ;

cmake.config.h.in

@@ -202,6 +202,9 @@
 /* Define to enable ARM NEON optimizations. */
 /* #undef HAVE_NEON */
 
+/* Define to enable RISC-V Vector optimizations. */
+/* #undef HAVE_RVV */
+
 /* Define if OpenMP is enabled */
 #cmakedefine HAVE_OPENMP
 

configure.ac

@@ -235,6 +235,12 @@ if test "$have_generic_simd256" = "yes"; then
 fi
 AM_CONDITIONAL(HAVE_GENERIC_SIMD256, test "$have_generic_simd256" = "yes")
 
+AC_ARG_ENABLE(rvv, [AC_HELP_STRING([--enable-rvv],[enable RISC-V V optimizations])], have_rvv=$enableval, have_rvv=no)
+if test "$have_rvv" = "yes"; then
+        AC_DEFINE(HAVE_RVV,1,[Define to enable RISC-V V optimizations.])
+fi
+AM_CONDITIONAL(HAVE_RVV, test "$have_rvv" = "yes")
+
 
 dnl FIXME:
 dnl AC_ARG_ENABLE(mips-ps, [AC_HELP_STRING([--enable-mips-ps],[enable MIPS pair-single optimizations])], have_mips_ps=$enableval, have_mips_ps=no)
@@ -770,6 +776,10 @@ AC_CONFIG_FILES([
    dft/simd/neon/Makefile
    dft/simd/generic-simd128/Makefile
    dft/simd/generic-simd256/Makefile
+   dft/simd/rvv128/Makefile
+   dft/simd/rvv256/Makefile
+   dft/simd/rvv512/Makefile
+   dft/simd/rvv1024/Makefile
 
    rdft/Makefile
    rdft/scalar/Makefile
@@ -790,6 +800,10 @@ AC_CONFIG_FILES([
    rdft/simd/neon/Makefile
    rdft/simd/generic-simd128/Makefile
    rdft/simd/generic-simd256/Makefile
+   rdft/simd/rvv128/Makefile
+   rdft/simd/rvv256/Makefile
+   rdft/simd/rvv512/Makefile
+   rdft/simd/rvv1024/Makefile
 
    reodft/Makefile
 

dft/codelet-dft.h

@@ -108,5 +108,9 @@ extern const solvtab X(solvtab_dft_vsx);
 extern const solvtab X(solvtab_dft_neon);
 extern const solvtab X(solvtab_dft_generic_simd128);
 extern const solvtab X(solvtab_dft_generic_simd256);
+extern const solvtab X(solvtab_dft_rvv128);
+extern const solvtab X(solvtab_dft_rvv256);
+extern const solvtab X(solvtab_dft_rvv512);
+extern const solvtab X(solvtab_dft_rvv1024);
 
 #endif				/* __DFT_CODELET_H__ */

dft/conf.c

@@ -85,4 +85,15 @@ void X(dft_conf_standard)(planner *p)
 #if HAVE_GENERIC_SIMD256
      X(solvtab_exec)(X(solvtab_dft_generic_simd256), p);
 #endif
+
+#if HAVE_RVV
+     if (X(have_simd_rvv)(128))
+          X(solvtab_exec)(X(solvtab_dft_rvv128), p);
+     if (X(have_simd_rvv)(256))
+          X(solvtab_exec)(X(solvtab_dft_rvv256), p);
+     if (X(have_simd_rvv)(512))
+          X(solvtab_exec)(X(solvtab_dft_rvv512), p);
+     if (X(have_simd_rvv)(1024))
+          X(solvtab_exec)(X(solvtab_dft_rvv1024), p);
+#endif
 }

dft/simd/Makefile.am

@@ -1,4 +1,4 @@
 AM_CPPFLAGS = -I $(top_srcdir)
-SUBDIRS = common sse2 avx avx-128-fma avx2 avx2-128 avx512 kcvi altivec vsx neon generic-simd128 generic-simd256
+SUBDIRS = common sse2 avx avx-128-fma avx2 avx2-128 avx512 kcvi altivec vsx neon generic-simd128 generic-simd256 rvv128 rvv256 rvv512 rvv1024
 EXTRA_DIST = n1b.h n1f.h n2b.h n2f.h n2s.h q1b.h q1f.h t1b.h t1bu.h	\
 t1f.h t1fu.h t2b.h t2f.h t3b.h t3f.h ts.h codlist.mk simd.mk

dft/simd/rvv1024/Makefile.am

@@ -0,0 +1,12 @@
+SIMD_HEADER=simd-support/simd-rvv1024.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv1024_codelets.la
+libdft_rvv1024_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

dft/simd/rvv128/Makefile.am

@@ -0,0 +1,12 @@
+SIMD_HEADER=simd-support/simd-rvv128.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv128_codelets.la
+libdft_rvv128_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

dft/simd/rvv256/Makefile.am

@@ -0,0 +1,12 @@
+SIMD_HEADER=simd-support/simd-rvv256.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv256_codelets.la
+libdft_rvv256_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

dft/simd/rvv512/Makefile.am

@@ -0,0 +1,12 @@
+SIMD_HEADER=simd-support/simd-rvv512.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv512_codelets.la
+libdft_rvv512_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

doc/install.texi

@@ -199,6 +199,7 @@ of the time).  @xref{Cycle Counters}.
 @code{--enable-altivec} (single),
 @code{--enable-vsx} (single, double),
 @code{--enable-neon} (single, double on aarch64),
+@code{--enable-rvv} (single, double on risc-v vector),
 @code{--enable-generic-simd128},
 and
 @code{--enable-generic-simd256}:

doc/intro.texi

@@ -18,7 +18,7 @@ transform (DFT) and various special cases thereof.
 
 @item  FFTW supports arbitrary multi-dimensional data.
 
-@item  FFTW supports the SSE, SSE2, AVX, AVX2, AVX512, KCVI, Altivec, VSX, and
+@item  FFTW supports the SSE, SSE2, AVX, AVX2, AVX512, KCVI, Altivec, VSX, RISC-V V, and
        NEON vector instruction sets.
 
 @item  FFTW includes parallel (multi-threaded) transforms

doc/other.texi

@@ -16,7 +16,7 @@ special operations supported by some processors to perform a single
 operation on several numbers (usually 2 or 4) simultaneously.  SIMD
 floating-point instructions are available on several popular CPUs:
 SSE/SSE2/AVX/AVX2/AVX512/KCVI on some x86/x86-64 processors, AltiVec and
-VSX on some POWER/PowerPCs, NEON on some ARM models.  FFTW can be
+VSX on some POWER/PowerPCs, NEON on some ARM models, V extension on some RISC-V models.  FFTW can be
 compiled to support the SIMD instructions on any of these systems.
 @cindex SIMD
 @cindex SSE

kernel/ifftw.h

@@ -104,7 +104,7 @@ extern void X(extract_reim)(int sign, R *c, R **r, R **i);
       defined(HAVE_KCVI) || \
       defined(HAVE_ALTIVEC) || defined(HAVE_VSX) || \
       defined(HAVE_MIPS_PS) || \
-      defined(HAVE_GENERIC_SIMD128) || defined(HAVE_GENERIC_SIMD256)
+      defined(HAVE_GENERIC_SIMD128) || defined(HAVE_GENERIC_SIMD256) || defined(HAVE_RVV)
 #define HAVE_SIMD 1
 #else
 #define HAVE_SIMD 0
@@ -119,6 +119,7 @@ extern int X(have_simd_avx512)(void);
 extern int X(have_simd_altivec)(void);
 extern int X(have_simd_vsx)(void);
 extern int X(have_simd_neon)(void);
+extern int X(have_simd_rvv)(int);
 
 /* forward declarations */
 typedef struct problem_s problem;

rdft/codelet-rdft.h

@@ -147,6 +147,10 @@ extern const solvtab X(solvtab_rdft_vsx);
 extern const solvtab X(solvtab_rdft_neon);
 extern const solvtab X(solvtab_rdft_generic_simd128);
 extern const solvtab X(solvtab_rdft_generic_simd256);
+extern const solvtab X(solvtab_rdft_rvv128);
+extern const solvtab X(solvtab_rdft_rvv256);
+extern const solvtab X(solvtab_rdft_rvv512);
+extern const solvtab X(solvtab_rdft_rvv1024);
 
 /* real-input & output DFT-like codelets (DHT, etc.) */
 typedef struct kr2r_desc_s kr2r_desc;

rdft/conf.c

@@ -102,4 +102,14 @@ void X(rdft_conf_standard)(planner *p)
 #if HAVE_GENERIC_SIMD256
      X(solvtab_exec)(X(solvtab_rdft_generic_simd256), p);
 #endif
+#if HAVE_RVV
+	 if (X(have_simd_rvv)(128))
+          X(solvtab_exec)(X(solvtab_rdft_rvv128), p);
+     if (X(have_simd_rvv)(256))
+          X(solvtab_exec)(X(solvtab_rdft_rvv256), p);
+     if (X(have_simd_rvv)(512))
+          X(solvtab_exec)(X(solvtab_rdft_rvv512), p);
+     if (X(have_simd_rvv)(1024))
+          X(solvtab_exec)(X(solvtab_rdft_rvv1024), p);
+#endif
 }

rdft/simd/Makefile.am

@@ -1,4 +1,4 @@
 
 AM_CPPFLAGS = -I $(top_srcdir)
-SUBDIRS = common sse2 avx avx-128-fma avx2 avx2-128 avx512 kcvi altivec vsx neon generic-simd128 generic-simd256
+SUBDIRS = common sse2 avx avx-128-fma avx2 avx2-128 avx512 kcvi altivec vsx neon generic-simd128 generic-simd256 rvv128 rvv256 rvv512 rvv1024
 EXTRA_DIST = hc2cbv.h hc2cfv.h codlist.mk simd.mk

rdft/simd/rvv1024/Makefile.am

@@ -0,0 +1,12 @@
+SIMD_HEADER=simd-support/simd-rvv1024.h
+
+include $(top_srcdir)/rdft/simd/codlist.mk
+include $(top_srcdir)/rdft/simd/simd.mk
+
+if HAVE_RVV
+
+noinst_LTLIBRARIES = librdft_rvv1024_codelets.la
+BUILT_SOURCES = $(EXTRA_DIST)
+librdft_rvv1024_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

rdft/simd/rvv128/Makefile.am

@@ -0,0 +1,12 @@
+SIMD_HEADER=simd-support/simd-rvv128.h
+
+include $(top_srcdir)/rdft/simd/codlist.mk
+include $(top_srcdir)/rdft/simd/simd.mk
+
+if HAVE_RVV
+
+noinst_LTLIBRARIES = librdft_rvv128_codelets.la
+BUILT_SOURCES = $(EXTRA_DIST)
+librdft_rvv128_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

rdft/simd/rvv256/Makefile.am

@@ -0,0 +1,12 @@
+SIMD_HEADER=simd-support/simd-rvv256.h
+
+include $(top_srcdir)/rdft/simd/codlist.mk
+include $(top_srcdir)/rdft/simd/simd.mk
+
+if HAVE_RVV
+
+noinst_LTLIBRARIES = librdft_rvv256_codelets.la
+BUILT_SOURCES = $(EXTRA_DIST)
+librdft_rvv256_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

rdft/simd/rvv512/Makefile.am

@@ -0,0 +1,12 @@
+SIMD_HEADER=simd-support/simd-rvv512.h
+
+include $(top_srcdir)/rdft/simd/codlist.mk
+include $(top_srcdir)/rdft/simd/simd.mk
+
+if HAVE_RVV
+
+noinst_LTLIBRARIES = librdft_rvv512_codelets.la
+BUILT_SOURCES = $(EXTRA_DIST)
+librdft_rvv512_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

simd-support/Makefile.am

@@ -11,5 +11,5 @@ avx512.c simd-avx512.h \
 kcvi.c simd-kcvi.h \
 altivec.c simd-altivec.h vsx.c simd-vsx.h \
 neon.c simd-neon.h \
-simd-generic128.h simd-generic256.h
-
+simd-generic128.h simd-generic256.h \
+rvv.c simd-rvv.h simd-rvv128.h simd-rvv256.h simd-rvv512.h simd-rvv1024.h

simd-support/rvv.c

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2003, 2007-14 Matteo Frigo
+ * Copyright (c) 2003, 2007-14 Massachusetts Institute of Technology
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+
+
+#include "kernel/ifftw.h"
+#include <riscv_vector.h>
+
+#if HAVE_RVV
+/* don't know how to autodetect RVV; assume it is present */
+  int X(have_simd_rvv)(int rs)
+  {
+       return vsetvlmax_e64m1() == (rs / 64);
+  }
+#endif

simd-support/simd-common.h

@@ -60,6 +60,14 @@
 #    define ALIGNMENT 16
 #    define ALIGNMENTA 16
 #  endif
+#elif defined(HAVE_RVV)
+#  if defined(FFTW_SINGLE)
+#    define ALIGNMENT 8
+#    define ALIGNMENTA 16
+#  else
+#    define ALIGNMENT 16
+#    define ALIGNMENTA 16
+#  endif
 #endif
 
 #if HAVE_SIMD