Merge branch 'main' of https://github.com/FPGAwars/iceSRegs

Author: Obijuan

README.md

@@ -810,6 +810,9 @@ For installing and using this colection in Icestudio follow these steps:
     * 30-Sys-SR
     * 31-Sys-SR
     * 32-Sys-SR
+  * **Sys-SR-basic**
+    * **Blocks**
+      * 02-Sys-SR-basic
   * **Sys-SR-ld**
     * 02-Sys-SR-ld
     * 03-Sys-SR-ld

locale/translation.js

@@ -1214,6 +1214,7 @@ gettext('SR-ld');
 gettext('SR-ld-rst');
 gettext('SR-rst');
 gettext('Sys-SR');
+gettext('Sys-SR-basic');
 gettext('Sys-SR-ld');
 gettext('Sys-SR-ld-rst');
 gettext('Sys-SR-rst');
@@ -1604,6 +1605,9 @@ gettext('31-Sys-SR: 31 bits system shift right register. Verilog implementation'
 gettext('32-Sys-SR');
 gettext('32-Sys-SR: 32 bits system shift right register. Verilog implementation');
 gettext('Blocks');
+gettext('02-Sys-SR-basic');
+gettext('02-Sys-SR-basic-block: Basic 2-bits System Shift register to the right. Block implementation 1');
+gettext('Blocks');
 gettext('02-Sys-SR-ld');
 gettext('02-Sys-SR-ld: 2 bits system shift right register with load input. Verilog implementation');
 gettext('03-Sys-SR-ld');