This repository hosts the RISC-V Lab, a collaborative educational project by Fraunhofer IMS in cooperation with the University of Duisburg-Essen.
The goal of this lab is to give students hands-on experience with RISC-V, an open and free instruction set architecture that is shaping the future of computing. Within this lab, students will explore a RISC-V-based platform implemented on the Digilent Nexy A7 FPGA development board using a fully open-source and royalty-free soft-core processor.
Initially, the setup is used much like a simple microcontroller platform - ideal for getting started with embedded programming and digital design. Later exercises may extend into system-level topics such as custom accelerators and interfaces, hardware/software co-design, and verification.
We welcome contributions! If you encounter issues or have suggestions, please use GitHub Issues or the Discussions board for feedback. Pull requests are highly appreciated! For academic or organizational inquiries, please contact the lab staff: 📫 riscv@uni-due.de
Clone this repository using git. Note that this repository uses submodules. Hence, you need to clone
recursively to include all submodules.
git clone --recurse-submodules https://github.com/Fraunhofer-IMS/riscv_lab.gitWarning
If you just use the Download button the submodules will not be included and have to be downloaded manually.
🔌 The vivado folder contains the actual AMD Vivado hardware design of the RISC-V
SoC implemented on the FPGA. Here you will also find documentation on the integrated peripherals
connected to the SoC. Tutorials also show you how to set up the Vivado project yourself.
💻 The eclipse folder provides a preconfigured Eclipse example project and
instructions on how to set up and configure Eclipse to start coding. The project features a simple
demo program and a hardware abstraction layer (HAL) for the basic on-board peripherals.
This project is released under the permissive BSD-3-clause license.
See LICENSE for more information.
Copyright (c) 2025 by Fraunhofer Institute for Microelectronic Circuits and Systems (Fraunhofer IMS).
Finkenstrasse 61, 47057 Duisburg, Germany.
https://ims.fraunhofer.de/en.html
- "Nexys" is a trademark of Digilent Inc.
- "Vivado" and "Artix" are trademarks of AMD Inc.
- "AXI", "AXI4", "AXI4-Lite" and "AXI4-Stream" are trademarks of Arm Holdings plc.
- "Windows" is a trademark of Microsoft Corporation.
- "ESP" is a trademark of Espressif Systems (Shanghai) Co., Ltd.
- "Eclipse" is trademark of the Eclipse Foundation.
- "PuTTY" copyright by Simon Tatham.
- "Tera Term" copyright by T. Teranishi.
- "Zadig" copyright by Pete Batard.
All further/unreferenced projects/products/brands belong to their according copyright holders. No copyright infringement intended.
This document contains links to the websites of third parties ("external links"). As the content of these websites is not under our control, we cannot assume any liability for such external content. In all cases, the provider of information of the linked websites is liable for the content and accuracy of the information provided. At the point in time when the links were placed, no infringements of the law were recognizable to us. As soon as an infringement of the law becomes known to us, we will immediately remove the link in question.