Various hardware improvements and fixed

hw/autocmd_wrap.sv

@@ -14,6 +14,7 @@ import sdhci_reg_pkg::*;
 module autocmd_wrap (
   input  logic clk_i,
   input  logic rst_ni,
+  input  logic clear_i,
   input  logic clk_en_p_i, // high before next sd_clk posedge
   input  logic clk_en_n_i, // high before next sd_clk negedge
   input  logic div_1_i,
@@ -55,13 +56,13 @@ module autocmd_wrap (
   ////////////////
 
   logic driver_cmd_queued_q, driver_cmd_queued_d;
-  `FF(driver_cmd_queued_q, driver_cmd_queued_d, '0, clk_i, rst_ni);
+  `FFARNC(driver_cmd_queued_q, driver_cmd_queued_d, clear_i, '0, clk_i, rst_ni);
 
   logic autocmd12_queued_q, autocmd12_queued_d;
-  `FF(autocmd12_queued_q, autocmd12_queued_d, '0, clk_i, rst_ni);
+  `FFARNC(autocmd12_queued_q, autocmd12_queued_d, clear_i, '0, clk_i, rst_ni);
 
   logic running_autocmd12_q, running_autocmd12_d;
-  `FF(running_autocmd12_q, running_autocmd12_d, '0, clk_i, rst_ni);
+  `FFARNC(running_autocmd12_q, running_autocmd12_d, clear_i, '0, clk_i, rst_ni);
 
   logic command_queued;
   assign command_queued = driver_cmd_queued_q || autocmd12_queued_q;
@@ -272,6 +273,7 @@ module autocmd_wrap (
   cmd_logic i_cmd_logic (
     .clk_i             (clk_i),
     .rst_ni            (rst_ni),
+    .clear_i           (clear_i),
     .clk_en_p_i        (clk_en_p_i),
     .clk_en_n_i        (clk_en_n_i),
     .div_1_i           (div_1_i),

hw/cmd_logic.sv

@@ -10,6 +10,7 @@
 module cmd_logic (
   input  logic clk_i,
   input  logic rst_ni,
+  input  logic clear_i,
   input  logic clk_en_p_i,
   input  logic clk_en_n_i,
   input  logic div_1_i,
@@ -48,7 +49,7 @@ module cmd_logic (
   } cmd_fsm_t;
 
   cmd_fsm_t cmd_state_q, cmd_state_d;
-  `FF(cmd_state_q, cmd_state_d, IDLE, clk_i, rst_ni);
+  `FFARNC(cmd_state_q, cmd_state_d, clear_i, IDLE, clk_i, rst_ni);
 
   // TODO: this forces a sleep cycle in between transactions. This might not
   // be ideal -> reduce sleep cycles in BUS_COOLDOWN by one
@@ -59,15 +60,15 @@ module cmd_logic (
   assign start_cmd = cmd_ready && cmd_valid_i;
 
   sdhci_pkg::cmd_t cmd_d, cmd_q;
-  `FFL(cmd_q, cmd_d, cmd_ready && cmd_valid_i, '0, clk_i, rst_ni);
+  `FFLARNC(cmd_q, cmd_d, cmd_ready && cmd_valid_i, clear_i, '0, clk_i, rst_ni);
   assign cmd_d = cmd_i;
 
   sdhci_pkg::cmd_arg_t cmd_arg_q, cmd_arg_d;
-  `FFL(cmd_arg_q, cmd_arg_d, cmd_ready && cmd_valid_i, '0, clk_i, rst_ni);
+  `FFLARNC(cmd_arg_q, cmd_arg_d, cmd_ready && cmd_valid_i, clear_i, '0, clk_i, rst_ni);
   assign cmd_arg_d = cmd_arg_i;
 
   sdhci_pkg::response_type_e response_type_q, response_type_d;
-  `FFL(response_type_q, response_type_d, cmd_ready && cmd_valid_i, sdhci_pkg::NO_RESPONSE, clk_i, rst_ni);
+  `FFLARNC(response_type_q, response_type_d, cmd_ready && cmd_valid_i, clear_i, sdhci_pkg::NO_RESPONSE, clk_i, rst_ni);
   assign response_type_d = response_type_i;
 
   // Electrical spec, 7.13.5; units are number of cycles
@@ -195,6 +196,7 @@ module cmd_logic (
   cmd_write i_cmd_write (
     .clk_i          (clk_i),
     .rst_ni         (rst_ni),
+    .clear_i        (clear_i),
 
     .clk_en_p_i     (clk_en_p_i),
     .clk_en_n_i     (clk_en_n_i),
@@ -213,6 +215,7 @@ module cmd_logic (
     .clk_i             (clk_i),
     .clk_en_i          (clk_en_p_i),
     .rst_ni            (rst_ni),
+    .clear_i           (clear_i),
     .cmd_i             (sd_bus_cmd_i),
     .long_rsp_i        (response_type_q == sdhci_pkg::RESPONSE_LENGTH_136),
     .start_listening_i (cmd_state_q == WAIT_RSP && (cycles_waiting == N_CR_MIN - 1)),
@@ -231,11 +234,11 @@ module cmd_logic (
   ) i_counter (
     .clk_i      (clk_i),
     .rst_ni     (rst_ni),
-    .clear_i    (1'b0),
+    .clear_i    (clear_i),
     .en_i       (clk_en_p_i),
     .load_i     (clear_cycle_counter),
     .down_i     (1'b0),
-    .d_i        ({'0, div_1_i}),
+    .d_i        ({6'b0, div_1_i}),
     .q_o        (cycles_waiting),
     .overflow_o ()
   );

hw/cmd_write/cmd_write.sv

@@ -12,6 +12,7 @@
 module cmd_write (
   input   logic         clk_i,
   input   logic         rst_ni,
+  input   logic         clear_i,
 
   input   logic         clk_en_p_i,
   input   logic         clk_en_n_i,
@@ -79,7 +80,7 @@ module cmd_write (
     endcase
   end : cmd_write_state_transition
 
-  `FFL(tx_state_q, tx_state_d, clk_en_p_i, READY, clk_i, rst_ni);
+  `FFLARNC(tx_state_q, tx_state_d, clk_en_p_i, clear_i, READY, clk_i, rst_ni);
 
   ///////////////
   // Data Path //
@@ -139,17 +140,18 @@ module cmd_write (
     endcase
   end : cmd_tx_datapath
 
-  `FFL(tx_ongoing_q, tx_ongoing_d, clk_en_p_i, '0, clk_i, rst_ni);
+  `FFLARNC(tx_ongoing_q, tx_ongoing_d, clk_en_p_i, clear_i, '0, clk_i, rst_ni);
 
 
   // delay to negative edge of clk
   always_ff @( negedge clk_i or negedge rst_ni) begin
     if(!rst_ni) sd_cmd_div1 <= 1'b1;
+    else if(clear_i) sd_cmd_div1 <= 1'b1;
     else sd_cmd_div1 <= sd_cmd;
   end
 
   // delay to negative edge of sd_clk
-  `FFL(sd_cmd_divn, sd_cmd, clk_en_n_i, '1, clk_i, rst_ni);
+  `FFLARNC(sd_cmd_divn, sd_cmd, clk_en_n_i, clear_i, '1, clk_i, rst_ni);
 
   // if freq of sd_clk and clk is same, delay to negative edge of clk
   // otherwise delay to negative edge of sd_clk
@@ -166,6 +168,7 @@ module cmd_write (
     .clk_i          (clk_i),
     .clk_en_i       (clk_en_p_i),
     .rst_ni         (rst_ni),
+    .clear_i        (clear_i),
     .par_write_en_i (par_write_en),
     .shift_en_i     (shift_en),
     .dat_par_i      (cmd_bits_47_to_8),
@@ -177,6 +180,7 @@ module cmd_write (
     .clk_i            (clk_i),
     .clk_en_i         (clk_en_p_i),
     .rst_ni           (rst_ni),
+    .clear_i          (clear_i),
     .shift_out_crc7_i (crc7_shift_en),
     .input_en_i       (shift_en), // only listen to input when shift reg outputs
     .dat_ser_i        (shift_reg_out),
@@ -189,7 +193,7 @@ module cmd_write (
   ) i_tx_bits_counter (
     .clk_i      (clk_i),
     .rst_ni     (rst_ni),
-    .clear_i    (tx_done_o), // clears to 0
+    .clear_i    (tx_done_o || clear_i), // clears to 0
     .en_i       (tx_ongoing_q && clk_en_p_i),
     .load_i     (1'b0), // always start at 0, no loading needed
     .down_i     (1'b0), // count up

hw/cmd_write/crc7_write.sv

@@ -15,6 +15,7 @@ module crc7_write (
   input   logic clk_i,
   input   logic clk_en_i,
   input   logic rst_ni,
+  input   logic clear_i,
 
   input   logic shift_out_crc7_i,
   input   logic input_en_i, //enable for data_ser_i
@@ -46,8 +47,8 @@ module crc7_write (
     end
   end
 
-  `FFL (lower_3_q, lower_3_d, clk_en_i, 0, clk_i, rst_ni);
-  `FFL (upper_4_q, upper_4_d, clk_en_i, 0, clk_i, rst_ni);
+  `FFLARNC (lower_3_q, lower_3_d, clk_en_i, clear_i, 0, clk_i, rst_ni);
+  `FFLARNC (upper_4_q, upper_4_d, clk_en_i, clear_i, 0, clk_i, rst_ni);
 
   //Output assignment
   assign crc_ser_o = upper_4_q[3];

hw/dat_buffer.sv

@@ -16,6 +16,7 @@ module dat_buffer #(
 ) (
   input  logic clk_i,
   input  logic rst_ni,
+  input  logic clear_i,
 
   input  logic read_operation_i,
   input  logic write_operation_i,
@@ -44,7 +45,7 @@ module dat_buffer #(
   assign block_size = MaxBlockBitSize'(reg2hw_i.block_size.transfer_block_size.q);
 
   logic [MaxBlockBitSize-1:0] current_word_counter_q, current_word_counter_d;
-  `FF (current_word_counter_q, current_word_counter_d, '0);
+  `FFARNC (current_word_counter_q, current_word_counter_d, clear_i, '0, clk_i, rst_ni);
 
   logic reg_empty;
   assign empty_o = reg_empty;
@@ -125,6 +126,7 @@ module dat_buffer #(
   ) i_sram_shift_reg (
     .clk_i,
     .rst_ni,
+    .clear_i,
 
     .en_i (enable_reg),
 

hw/dat_read/crc16_read.sv

@@ -12,6 +12,7 @@ module crc16_read (
   input   logic   clk_i,
   input   logic   sd_clk_en_i,
   input   logic   rst_ni,
+  input   logic   clear_i,
 
   input   logic   shift_in_i,
 
@@ -41,7 +42,7 @@ module crc16_read (
     end
   end
 
-  `FFL ( lower_5_q,  lower_5_d, sd_clk_en_i, '0);
-  `FFL (middle_7_q, middle_7_d, sd_clk_en_i, '0);
-  `FFL ( upper_4_q,  upper_4_d, sd_clk_en_i, '0);
+  `FFLARNC ( lower_5_q,  lower_5_d, sd_clk_en_i, clear_i, '0, clk_i, rst_ni);
+  `FFLARNC (middle_7_q, middle_7_d, sd_clk_en_i, clear_i, '0, clk_i, rst_ni);
+  `FFLARNC ( upper_4_q,  upper_4_d, sd_clk_en_i, clear_i, '0, clk_i, rst_ni);
 endmodule

hw/dat_read/dat_read.sv

@@ -16,6 +16,7 @@ module dat_read #(
   input  logic       clk_i,
   input  logic       sd_clk_en_i,
   input  logic       rst_ni,
+  input  logic       clear_i,
   input  logic [3:0] dat_i,
 
   input  logic                       start_i,
@@ -43,10 +44,10 @@ module dat_read #(
   } dat_rx_state_e;
 
   dat_rx_state_e state_q, state_d;
-  `FF (state_q, state_d, IDLE);
+  `FFARNC (state_q, state_d, clear_i, IDLE, clk_i, rst_ni);
 
   logic [CounterWidth-1:0] counter_q, counter_d;
-  `FFL (counter_q, counter_d, sd_clk_en_i, 0);
+  `FFLARNC (counter_q, counter_d, sd_clk_en_i, clear_i, 0, clk_i, rst_ni);
 
   logic [CounterWidth-1:0] required_clock_count;
   assign required_clock_count = bus_width_is_4_i ? 2*block_size_i : 8*block_size_i;
@@ -92,7 +93,7 @@ module dat_read #(
   logic calculate_crc;
   logic [3:0] crc_errors;
   logic [31:0] data_buildup_q, data_buildup_d;
-  `FFL (data_buildup_q, data_buildup_d, sd_clk_en_i, 0);
+  `FFLARNC (data_buildup_q, data_buildup_d, sd_clk_en_i, clear_i, 0, clk_i, rst_ni);
 
   always_comb begin
     counter_d      = '0;
@@ -188,6 +189,7 @@ module dat_read #(
       .clk_i,
       .sd_clk_en_i,
       .rst_ni,
+      .clear_i,
 
       .shift_in_i (calculate_crc),
 

hw/dat_wrap.sv

@@ -19,6 +19,7 @@ module dat_wrap #(
   input  logic sd_clk_en_n_i,
   input  logic div_1_i,
   input  logic rst_ni,
+  input  logic clear_i,
 
   input  logic [3:0] dat_i,
   output logic       dat_en_o,
@@ -59,7 +60,7 @@ module dat_wrap #(
   logic timeout_elapsed;
 
   logic [15:0] transmitted_block_counter_q, transmitted_block_counter_d;
-  `FF (transmitted_block_counter_q, transmitted_block_counter_d, '0);
+  `FFARNC (transmitted_block_counter_q, transmitted_block_counter_d, clear_i, '0, clk_i, rst_ni);
 
   typedef enum logic [1:0] {
     READY,
@@ -98,16 +99,16 @@ module dat_wrap #(
   } write_state_e;
 
   dat_state_e dat_state_q, dat_state_d;
-  `FF (dat_state_q, dat_state_d, READY, clk_i, rst_ni);
+  `FFARNC (dat_state_q, dat_state_d, clear_i, READY, clk_i, rst_ni);
 
   busy_state_e busy_state_q, busy_state_d;
-  `FF (busy_state_q, busy_state_d, BUSY_WAIT_FOR_CMD, clk_i, rst_ni);
+  `FFARNC (busy_state_q, busy_state_d, clear_i, BUSY_WAIT_FOR_CMD, clk_i, rst_ni);
 
   read_state_e read_state_q, read_state_d;
-  `FF (read_state_q, read_state_d, WAIT_FOR_CMD, clk_i, rst_ni);
+  `FFARNC (read_state_q, read_state_d, clear_i, WAIT_FOR_CMD, clk_i, rst_ni);
 
   write_state_e write_state_q, write_state_d;
-  `FF (write_state_q, write_state_d, WAIT_FOR_RSP, clk_i, rst_ni);
+  `FFARNC (write_state_q, write_state_d, clear_i, WAIT_FOR_RSP, clk_i, rst_ni);
 
   always_comb begin : main_fsm
     dat_state_d = dat_state_q;
@@ -154,10 +155,10 @@ module dat_wrap #(
   assign sd_busy_o = dat_state_q == BUSY;
 
   logic [1:0] busy_counter_q, busy_counter_d;
-  `FF(busy_counter_q, busy_counter_d, 2'b0, clk_i, rst_ni);
+  `FFARNC(busy_counter_q, busy_counter_d, clear_i, 2'b0, clk_i, rst_ni);
 
   logic busy_saw_response_q, busy_saw_response_d;
-  `FF(busy_saw_response_q, busy_saw_response_d, 1'b0, clk_i, rst_ni);
+  `FFARNC(busy_saw_response_q, busy_saw_response_d, clear_i, 1'b0, clk_i, rst_ni);
 
   always_comb begin : busy_fsm
     busy_state_d        = busy_state_q;
@@ -500,6 +501,7 @@ module dat_wrap #(
   ) i_dat_buffer (
     .clk_i,
     .rst_ni,
+    .clear_i,
 
     .read_operation_i  (reg2hw_i.present_state.read_transfer_active.q),
     .write_operation_i (reg2hw_i.present_state.write_transfer_active.q),
@@ -527,6 +529,7 @@ module dat_wrap #(
     .clk_i,
     .sd_clk_en_i   (sd_clk_en_p_i),
     .rst_ni,
+    .clear_i,
     .dat_i,
 
     .start_i          (start_read),
@@ -551,6 +554,7 @@ module dat_wrap #(
     .sd_clk_en_n_i  (sd_clk_en_n_i),
     .div_1_i        (div_1_i),
     .rst_ni,
+    .clear_i,
     .dat0_i         (dat_i[0]),
     .dat_o,
     .dat_en_o,

hw/dat_write/crc16_write.sv

@@ -12,6 +12,7 @@ module crc16_write (
   input logic clk_i,
   input logic sd_clk_en_i,
   input logic rst_ni,
+  input logic clear_i,
 
   input logic shift_out_crc16_i,
   input logic dat_ser_i,
@@ -48,9 +49,9 @@ module crc16_write (
     end
   end
 
-  `FFL ( upper_4_q,  upper_4_d, sd_clk_en_i, 0);
-  `FFL (middle_7_q, middle_7_d, sd_clk_en_i, 0);
-  `FFL ( lower_5_q,  lower_5_d, sd_clk_en_i, 0);
+  `FFLARNC ( upper_4_q,  upper_4_d, sd_clk_en_i, clear_i, 0, clk_i, rst_ni);
+  `FFLARNC (middle_7_q, middle_7_d, sd_clk_en_i, clear_i, 0, clk_i, rst_ni);
+  `FFLARNC ( lower_5_q,  lower_5_d, sd_clk_en_i, clear_i, 0, clk_i, rst_ni);
 
 `ifdef VERILATOR
   logic [15:0] crc;