RISC-V: refine fpu offset according to portFPU_REG_SIZE #1256
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Signed-off-by: wangfei_chen <[email protected]>
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aggarg
approved these changes
Mar 13, 2025
kar-rahul-aws
approved these changes
Mar 13, 2025
tony-josi-aws
approved these changes
Mar 13, 2025
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Description
About the size of FPU, each register in Fextension is 32 bits and 64 bits in D-extension. Use portFPU_REG_SIZE to keep offset correct.
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