FPGA-course

Logic Circuits and Computer Architecture Laboratory

About the Course

The Logic Circuits and Computer Architecture Laboratory course is designed to provide hands-on experience with digital logic circuits and computer architecture concepts. The course covers topics such as combinational and sequential logic design, memory systems, processor architecture, and more. The course includes practical projects using both VHDL (VHSIC Hardware Description Language) and Verilog, two of the most widely-used hardware description languages.

Repository Contents

The repository includes the following:

• VHDL and Verilog source code files for various laboratory experiments.
• Documentation and explanations for each experiment.
• Supplementary materials and resources.

How to Use

To use the code in this repository, follow these steps:

1. Clone the repository to your local machine using the following command:
2. Navigate to the specific experiment directory you are interested in.
3. Open the VHDL or Verilog source code file using a VHDL/Verilog simulator or an IDE like ModelSim, Vivado, or VS Code with relevant extensions.
4. Follow the instructions provided in the documentation to run and test the experiment.

Using VHDL and Verilog with Recommended Tools

This repository includes examples in both VHDL and Verilog. To work with the code effectively, we recommend using the following tools and extensions:

Visual Studio Code Extensions

To work efficiently with both VHDL and Verilog, consider installing the following extensions in VS Code:

1. VHDL Extensions

• VHDL Support

  • Provides syntax highlighting, linting, and code snippets for VHDL.
  • To install: Open VS Code → Go to Extensions view (Ctrl+Shift+X) → Search for "VHDL Support" → Click "Install".

• VHDL Linter

  • Offers error detection, code analysis, and additional features for VHDL.
  • Follow the same installation steps as above, searching for "VHDL Linter".

2. Verilog Extensions

• Opendigital js

  • Enhances VS Code for digital design and Verilog HDL, offering syntax highlighting, code formatting, and linting.
  • To install: Open VS Code → Go to Extensions view (Ctrl+Shift+X) → Search for "Opendigital js" → Click "Install".

• Verilog HDL

  • Provides support for Verilog with features like syntax highlighting, code snippets, and linting.
  • To install: Follow the same installation steps, searching for "Verilog HDL".

Simulation and Synthesis Tools

For simulation and testing of VHDL and Verilog code, we recommend the following tools:

• ModelSim
  • A popular simulator for both VHDL and Verilog, providing a user-friendly interface for compiling and simulating hardware designs.
• Vivado
  • An integrated design environment for VHDL/Verilog and FPGA design, offering simulation, synthesis, and implementation tools.

Running the Code

1. Choose the relevant source code file (VHDL or Verilog) for the experiment you wish to work on.
2. Use a VHDL/Verilog-compatible simulator (e.g., ModelSim or Vivado) to compile and simulate the design.
3. Review the simulation results and waveforms to understand the behavior of the digital circuit.
4. Modify the code as necessary to experiment with different configurations and designs.

Contributing

If you would like to contribute to this repository, you can follow these steps:

1. Fork the repository to your own GitHub account.
2. Create a new branch with a descriptive name for your changes.
3. Make the necessary modifications and improvements.
4. Commit and push your changes to your forked repository.
5. Submit a pull request, explaining the changes you have made.