@@ -374,13 +374,12 @@ enum CacheCoherencyUsageFlags : uint32
374374 CoherMemory = 0x00020000 , // /< Data read or written directly from/to memory
375375 CoherSampleRate = 0x00040000 , // /< CmdBindSampleRateImage() source.
376376 CoherPresent = 0x00080000 , // /< Source of present.
377- CoherCp = CoherTimestamp, // /< HW Command Processor (CP) encompassing the front - end command
378- // / processing of any queue, including SDMA.
377+ CoherCp = 0x00200000 , // /< HW Command Processor (CP) encompassing the front - end command
378+ CoherAllUsages = 0x003FFFFF , // /< processing of any queue, including SDMA.
379+
379380 CoherShader = CoherShaderRead | CoherShaderWrite,
380381 CoherCopy = CoherCopySrc | CoherCopyDst,
381382 CoherResolve = CoherResolveSrc | CoherResolveDst,
382-
383- CoherAllUsages = 0x000FFFFF ,
384383};
385384
386385// / Bitmask values for the flags parameter of ICmdBuffer::CmdClearColorImage().
@@ -1077,13 +1076,15 @@ struct ImgBarrier
10771076 // / engines up to this point. These masks imply the previous compression state. No
10781077 // / usage flags should ever be set in oldLayout.usages that correspond to usages
10791078 // / that are not supported by the engine that is performing the transition. The
1080- // / engine type performing the transition must be set in oldLayout.engines.
1079+ // / engine type performing the transition must be set in oldLayout.engines. Can set
1080+ // / both oldLayout and newLayout to zero value for no layout transition case.
10811081 ImageLayout newLayout; // /< Specifies the upcoming image layout based on bitmasks of allowed operations and
10821082 // / engines after this point. These masks imply the upcoming compression state.
10831083 // / point. A difference between oldLayoutUsageMask and newLayoutUsageMask may result
10841084 // / in a decompression. PAL's implementation will ensure the results of any layout
10851085 // / operations are consistent with the requested availability and visibility
1086- // / operations.
1086+ // / operations. Can set both oldLayout and newLayout to zero value for no layout
1087+ // / transition case.
10871088
10881089 // / Specifies a custom sample pattern over a 2x2 pixel quad. The position for each sample is specified on a grid
10891090 // / where the pixel center is <0,0>, the top left corner of the pixel is <-8,-8>, and <7,7> is the maximum valid
@@ -2865,9 +2866,6 @@ class ICmdBuffer : public IDestroyable
28652866 // / CmdAcquire() call is expected to wait on one or a list of such synchronization tokens and perform any necessary
28662867 // / visibility operations and/or layout transitions that could not be predicted at release-time.
28672868 // /
2868- // / @note Not all hardware can support the acquire/release mechanism with good performance. This call is only
2869- // / valid if supportReleaseAcquireInterface is set in the GFXIP properties section of @ref DeviceProperties.
2870- // /
28712869 // / @param [in] releaseInfo Describes the synchronization scope, availability operations, and required layout
28722870 // / transitions.
28732871 // / @returns Synchronization token for the release operation. Pass this token to CmdAcquire to confirm completion.
@@ -2881,9 +2879,6 @@ class ICmdBuffer : public IDestroyable
28812879 // / Performs the acquire portion of an acquire/release-based barrier. This acquire a set of resources for a new
28822880 // / set of usages, assuming CmdRelease() was called to release access for the resource's past usage.
28832881 // /
2884- // / @note Not all hardware can support the acquire/release mechanism with good performance. This call is only
2885- // / valid if supportReleaseAcquireInterface is set in the GFXIP properties section of @ref DeviceProperties.
2886- // /
28872882 // / Conceptually, this method will:
28882883 // / - Ensure all specified resources are visible in memory. The visibility operation will invalidate all
28892884 // / relevant caches above the last-level-cache.
@@ -2919,9 +2914,6 @@ class ICmdBuffer : public IDestroyable
29192914 // / CmdAcquireEvent() call is expected to wait on this event and perform any necessary visibility operations and/or
29202915 // / layout transitions that could not be predicted at release-time.
29212916 // /
2922- // / @note Not all hardware can support the acquire/release mechanism with good performance. This call is only
2923- // / valid if supportReleaseAcquireInterface is set in the GFXIP properties section of @ref DeviceProperties.
2924- // /
29252917 // / @param [in] releaseInfo Describes the synchronization scope, availability operations, and required layout
29262918 // / transitions.
29272919 // / @param [in] pGpuEvent Event to be signaled once the release has completed. Must be a valid (non-null) GPU
@@ -2941,9 +2933,6 @@ class ICmdBuffer : public IDestroyable
29412933 // / relevant caches above the last-level-cache.
29422934 // / - Perform any requested layout transitions.
29432935 // /
2944- // / @note Not all hardware can support the acquire/release mechanism with good performance. This call is only
2945- // / valid if supportReleaseAcquireInterface is set in the GFXIP properties section of @ref DeviceProperties.
2946- // /
29472936 // / @param [in] acquireInfo Describes the synchronization scope, visibility operations, and the required layout
29482937 // / layout transitions.
29492938 // / @param [in] gpuEventCount Number of entries in pGpuEvents.
@@ -2963,9 +2952,6 @@ class ICmdBuffer : public IDestroyable
29632952 // /
29642953 // / Effectively equivalent to @ref ICmdBuffer::CmdBarrier.
29652954 // /
2966- // / @note Not all hardware can support the acquire/release mechanism with good performance. This call is only
2967- // / valid if supportReleaseAcquireInterface is set in the GFXIP properties section of @ref DeviceProperties.
2968- // /
29692955 // / @param [in] barrierInfo Describes the synchronization scopes, availability/visibility operations, and the
29702956 // / required layout transitions.
29712957 virtual void CmdReleaseThenAcquire (
@@ -3370,6 +3356,11 @@ class ICmdBuffer : public IDestroyable
33703356 // / The source and destination images must to be of the same type (1D, 2D or 3D), or optionally 2D and 3D with the
33713357 // / number of slices matching the depth. MSAA source and destination images must have the same number of samples.
33723358 // /
3359+ // / Each region must satisfy these restrictions.
3360+ // / - srcOffset >= 0 and dstOffset >= 0
3361+ // / - srcOffset + extent <= srcSubres's extent
3362+ // / - dstOffset + extent <= dstSubres's extent
3363+ // /
33733364 // / Images copied via this function must have x/y/z offsets and width/height/depth extents aligned to the minimum
33743365 // / tiled copy alignment specified in @ref DeviceProperties for the engine this function is executed on. Note that
33753366 // / the DMA engine supports tiled copies regardless of the alignment; the reported minimum tiled copy alignments
@@ -3416,6 +3407,8 @@ class ICmdBuffer : public IDestroyable
34163407 // / The source memory offset has to be aligned to the smaller of the copied texel size or 4 bytes. A destination
34173408 // / subresource cannot be present more than once per CmdCopyMemoryToImage() call.
34183409 // /
3410+ // / Each region's imageOffset must be >= 0 and imageOffset + imageExtent must be <= imageSubres's extent.
3411+ // /
34193412 // / This function requires use of the following barrier flags:
34203413 // / - PipelineStage: @ref PipelineStageBlt
34213414 // / - CacheCoherency: @ref CoherCopySrc for the source and @ref CoherCopyDst for the destination.
@@ -3445,6 +3438,8 @@ class ICmdBuffer : public IDestroyable
34453438 // / The destination memory offset has to be aligned to the smaller of the copied texel size or 4 bytes. A
34463439 // / destination region cannot be present more than once per CmdCopyImageToMemory() call.
34473440 // /
3441+ // / Each region's imageOffset must be >= 0 and imageOffset + imageExtent must be <= imageSubres's extent.
3442+ // /
34483443 // / This function requires use of the following barrier flags:
34493444 // / - PipelineStage: @ref PipelineStageBlt
34503445 // / - CacheCoherency: @ref CoherCopySrc for the source and @ref CoherCopyDst for the destination.
@@ -3478,6 +3473,8 @@ class ICmdBuffer : public IDestroyable
34783473 // / The source memory offset has to be aligned to the smaller of the copied texel size or 4 bytes. A destination
34793474 // / subresource cannot be present more than once per CmdCopyMemoryToTiledImage() call.
34803475 // /
3476+ // / Each region's imageOffset must be >= 0 and imageOffset + imageExtent must be <= imageSubres's extent.
3477+ // /
34813478 // / This function requires use of the following barrier flags:
34823479 // / - PipelineStage: @ref PipelineStageBlt
34833480 // / - CacheCoherency: @ref CoherCopySrc for the source and @ref CoherCopyDst for the destination.
@@ -3511,6 +3508,8 @@ class ICmdBuffer : public IDestroyable
35113508 // / The destination memory offset has to be aligned to the smaller of the copied texel size or 4 bytes. A
35123509 // / destination region cannot be present more than once per CmdCopyTiledImageToMemory() call.
35133510 // /
3511+ // / Each region's imageOffset must be >= 0 and imageOffset + imageExtent must be <= imageSubres's extent.
3512+ // /
35143513 // / This function requires use of the following barrier flags:
35153514 // / - PipelineStage: @ref PipelineStageBlt
35163515 // / - CacheCoherency: @ref CoherCopySrc for the source and @ref CoherCopyDst for the destination.
@@ -4033,6 +4032,7 @@ class ICmdBuffer : public IDestroyable
40334032 const IGpuEvent& gpuEvent,
40344033 uint32 stageMask) = 0;
40354034
4035+ #if PAL_CLIENT_INTERFACE_MAJOR_VERSION < 900
40364036 // / Puts the specified GPU event into the _set_ state when all previous GPU work reaches the specified point in the
40374037 // / pipeline.
40384038 // /
@@ -4062,6 +4062,7 @@ class ICmdBuffer : public IDestroyable
40624062 const IGpuEvent& gpuEvent,
40634063 HwPipePoint resetPoint)
40644064 { CmdResetEvent (gpuEvent, HwPipePointToStage[resetPoint]); }
4065+ #endif
40654066
40664067 // / Predicate the subsequent jobs in the command buffer if the event is set.
40674068 // /
@@ -4202,6 +4203,7 @@ class ICmdBuffer : public IDestroyable
42024203 ImmediateDataWidth dataSize,
42034204 gpusize address) = 0;
42044205
4206+ #if PAL_CLIENT_INTERFACE_MAJOR_VERSION < 900
42054207 // / Writes a HwPipePostPrefetch or HwPipeBottom timestamp to the specified memory location.
42064208 // /
42074209 // / The timestamp data is a 64-bit value that increments once per clock. timestampFrequency in DeviceProperties
@@ -4249,6 +4251,7 @@ class ICmdBuffer : public IDestroyable
42494251 ImmediateDataWidth dataSize,
42504252 gpusize address)
42514253 { CmdWriteImmediate (HwPipePointToStage[pipePoint], data, dataSize, address); }
4254+ #endif
42524255
42534256 // / Loads the current stream-out buffer-filled-sizes stored on the GPU from memory, typically from a target of a
42544257 // / prior CmdSaveBufferFilledSizes() call.
@@ -4911,6 +4914,7 @@ class ICmdBuffer : public IDestroyable
49114914 // / For non-top-layer objects, this will point to the layer above the current object.
49124915 void * m_pClientData;
49134916
4917+ #if PAL_CLIENT_INTERFACE_MAJOR_VERSION < 900
49144918 // / @internal Some back-compat glue for some of the HwPipePoint interfaces in this file.
49154919 static constexpr uint32 HwPipePointToStage[] =
49164920 {
@@ -4928,6 +4932,7 @@ class ICmdBuffer : public IDestroyable
49284932 PipelineStageBlt, // HwPipePostBlt = 0x6
49294933 PipelineStageBottomOfPipe, // HwPipeBottom = 0x7
49304934 };
4935+ #endif
49314936};
49324937
49334938} // Pal
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