Name		Name	Last commit message	Last commit date
compiler		compiler
kernel_verilog		kernel_verilog
runtime		runtime
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md

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gnn-acceleration-framework-with-FPGA

The models can be compiled by compiler, the runtime is generated and managed by Vitis, and the hardware is implemented on Xilinx U280 FPGA board.

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including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware verilog code that can be implemented on FPGA

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