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9f2485b
Update README.md
yazdan2727 Jul 3, 2024
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yazdan2727 Jul 3, 2024
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163 changes: 151 additions & 12 deletions Fixed_Point_Unit.v
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Original file line number Diff line number Diff line change
Expand Up @@ -21,11 +21,11 @@ module Fixed_Point_Unit
always @(*)
begin
case (operation)
`FPU_ADD : begin result <= operand_1 + operand_2; ready <= 1; end
`FPU_SUB : begin result <= operand_1 - operand_2; ready <= 1; end
`FPU_MUL : begin result <= product[WIDTH + FBITS - 1 : FBITS]; ready <= product_ready; end
`FPU_SQRT : begin result <= root; ready <= root_ready; end
default : begin result <= 'bz; ready <= 0; end
`FPU_ADD : begin result = operand_1 + operand_2; ready = 1; end
`FPU_SUB : begin result = operand_1 - operand_2; ready = 1; end
`FPU_MUL : begin result = product[WIDTH + FBITS - 1 : FBITS]; ready = product_ready; end
`FPU_SQRT : begin result = root; ready = root_ready; end
default : begin result = 'bz; ready = 0; end
endcase
end

Expand All @@ -40,9 +40,87 @@ module Fixed_Point_Unit
reg [WIDTH - 1 : 0] root;
reg root_ready;

/*
* Describe Your Square Root Calculator Circuit Here.
*/
reg [1 : 0] square_root_stage;
reg [1 : 0] next_square_root_stage;

always @(posedge clk)
begin
if (operation == `FPU_SQRT) square_root_stage <= next_square_root_stage;
else
begin
square_root_stage <= 2'b00;
root_ready <= 0;
end
end

always @(*)
begin
next_square_root_stage <= 'bz;
case (square_root_stage)
2'b00 : begin sqrt_start <= 0; next_square_root_stage <= 2'b01; end
2'b01 : begin sqrt_start <= 1; next_square_root_stage <= 2'b10; end
2'b10 : begin sqrt_start <= 0; next_square_root_stage <= 2'b10; end
endcase
end
reg sqrt_start;
reg sqrt_busy;

reg [WIDTH - 1 : 0] x, x_next;
reg [WIDTH - 1 : 0] q, q_next;
reg [WIDTH + 1 : 0] ac, ac_next;
reg [WIDTH + 1 : 0] test_res;

reg valid;

localparam ITER = (WIDTH + FBITS) >> 1;
reg [4 : 0] i = 0;

always @(*)
begin
test_res = ac - {q, 2'b01};

if (test_res[WIDTH + 1] == 0)
begin
{ac_next, x_next} = {test_res[WIDTH - 1 : 0], x, 2'b0};
q_next = {q[WIDTH - 2 : 0], 1'b1};
end
else
begin
{ac_next, x_next} = {ac[WIDTH - 1 : 0], x, 2'b0};
q_next = q << 1;
end
end

always @(posedge clk)
begin
if (sqrt_start)
begin
sqrt_busy <= 1;
root_ready <= 0;
i <= 0;
q <= 0;
{ac, x} <= {{WIDTH{1'b0}}, operand_1, 2'b0};
end

else if (sqrt_busy)
begin
if (i == ITER-1)
begin // we're done
sqrt_busy <= 0;
root_ready <= 1;
root <= q_next;
end

else
begin // next iteration
i <= i + 1;
x <= x_next;
ac <= ac_next;
q <= q_next;
root_ready <= 0;
end
end
end

// ------------------ //
// Multiplier Circuit //
Expand All @@ -66,10 +144,71 @@ module Fixed_Point_Unit
reg [31 : 0] partialProduct3;
reg [31 : 0] partialProduct4;

/*
* Describe Your 32-bit Multiplier Circuit Here.
*/

reg [2 : 0] multiplication_stage;
reg [2 : 0] next_multiplication_stage;

always @(posedge clk)
begin
if (operation == `FPU_MUL) multiplication_stage <= next_multiplication_stage;
else multiplication_stage <= 'b0;
end

always @(*)
begin
next_multiplication_stage <= 'bz;
case (multiplication_stage)
3'b000 :
begin
product_ready <= 0;

multiplierCircuitInput1 <= 'bz;
multiplierCircuitInput2 <= 'bz;

partialProduct1 <= 'bz;
partialProduct2 <= 'bz;
partialProduct3 <= 'bz;
partialProduct4 <= 'bz;

next_multiplication_stage <= 3'b001;
end
3'b001 :
begin
multiplierCircuitInput1 <= operand_1[15 : 0];
multiplierCircuitInput2 <= operand_2[15 : 0];
partialProduct1 <= multiplierCircuitResult;
next_multiplication_stage <= 3'b010;
end
3'b010 :
begin
multiplierCircuitInput1 <= operand_1[31 : 16];
multiplierCircuitInput2 <= operand_2[15 : 0];
partialProduct2 <= multiplierCircuitResult;
next_multiplication_stage <= 3'b011;
end
3'b011 :
begin
multiplierCircuitInput1 <= operand_1[15 : 0];
multiplierCircuitInput2 <= operand_2[31 : 16];
partialProduct3 <= multiplierCircuitResult;
next_multiplication_stage <= 3'b100;
end
3'b100 :
begin
multiplierCircuitInput1 <= operand_1[31 : 16];
multiplierCircuitInput2 <= operand_2[31 : 16];
partialProduct4 <= multiplierCircuitResult;
next_multiplication_stage <= 3'b101;
end
3'b101 :
begin
product <= partialProduct1 + (partialProduct2 << 16) + (partialProduct3 << 16) + (partialProduct4 << 32);
next_multiplication_stage <= 3'b000;
product_ready <= 1;
end

default: next_multiplication_stage <= 3'b000;
endcase
end
endmodule

module Multiplier
Expand Down
4 changes: 2 additions & 2 deletions Fixed_Point_Unit.vcd
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
$date
Tue Jun 04 00:34:50 2024
Tue Jul 02 23:31:19 2024
$end
$version
Icarus Verilog
Expand Down Expand Up @@ -611,4 +611,4 @@ x$
x"
bx !
$end
1$
1$
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