PBL

Error control coding (Encoder) in digital communication for Tsunami Early warning System using verilog

Project Overview

This repository contains Verilog implementations and testbenches for hardware blocks used in an LDPC-like encoding flow for disaster-management communication systems.

The project focuses on:

• One-hot phase generation
• Termination bit generation
• Code bit generation
• Information register control

These files are designed for functional simulation using Icarus Verilog and waveform inspection with GTKWave.

Repository Structure

• src/
  • information_register.v
  • code_bit_generation.v
  • one_hot_encoded_phase_generation.v
  • termination.v
• test/
  • information_register_tb.v
  • code_bit_generation_tb.v
  • one_hot_encoded_phase_generation_tb.v
  • termination_tb.v
• README.md
• waveform and simulation files generated by running the tests.

Prerequisites

Install these tools before running the simulations:

1. Icarus Verilog

   • Windows installer: https://iverilog.org
   • Linux: sudo apt install iverilog

2. GTKWave (optional, for waveform viewing)

   • Windows installer: http://gtkwave.sourceforge.net/

How to Run Each Simulation

Open a terminal in and enter PBL and run the following commands for each module.

1. Information Register

iverilog -o information_register.vvp src/information_register.v test/information_register_tb.v
vvp information_register.vvp

If the testbench generates wave.vcd, open it with:

gtkwave wave.vcd

2. Code Bit Generation

iverilog -o code_bit_generation.vvp src/code_bit_generation.v test/code_bit_generation_tb.v
vvp code_bit_generation.vvp

If the testbench writes a VCD file (for example code_bit_gen.vcd), open it with:

gtkwave code_bit_gen.vcd

3. One-Hot Encoded Phase Generation

iverilog -o one_hot_encoded_phase_generation.vvp src/one_hot_encoded_phase_generation.v test/one_hot_encoded_phase_generation_tb.v
vvp one_hot_encoded_phase_generation.vvp

Open the generated waveform file if available:

gtkwave dump.vcd

4. Termination Bit Generation

iverilog -o termination.vvp src/termination.v test/termination_tb.v
vvp termination.vvp

If the testbench produces a VCD file such as termination.vcd, open it with:

gtkwave termination.vcd

Recommended Sequence

Run the simulations in this order for a logical progression through the design:

1. Information register
2. Code bit generation
3. One-hot encoded phase generation
4. Termination bit generation

Waveform Viewing with GTKWave

1. Run the simulation.
2. Confirm the .vcd file exists in the repository root.
3. Open it with gtkwave:

gtkwave <filename>.vcd

If gtkwave is not installed, download and install it first.

Notes

• If a testbench does not generate a VCD file, use the printed vvp output to verify behavior.
• If you need waveform output, add $dumpfile("<name>.vcd"); and $dumpvars(0, <testbench_module>); to the testbench.

Known Issues

• This repository is intended for simulation and functional verification.
• FPGA implementation and real-time input sources are not included.
• Some modules may require additional development for synthesis or deployment.