2020 course: vlsi digital signal processing Tool
- Simulator: Modelsim
- FPGA: Xilinx PYNQ-Z2
- Xilinx Vivado
| Lab | Detail | Document |
|---|---|---|
| Lab 1 | simple led controller | lab1 document |
| Lab 2 | 4-bit RCA | lab2 document |
| Lab 3 | 8-bit Baugh–Wooley Array Multiplier | lab3 document |
| Lab 4 | 4-bit Counter Design | lab4 document |
| Lab 5 | Memory RW Design | lab5 document |
| Lab 6 | 4-bit RCA with timing constraints | |
| Lab 7 | multiplier design with timing constraints | lab7 document |
| Lab 8 | fir filter design | lab8 document |
| Lab 9 | 16bit up down counter design | lab9 document |
| Lab 10 | 7-tap fir filter design | lab10 document |
| Lab 11 | matrix inner product | lab11 document |
| Lab 12 | Matrix inner product with Distributed Arithmetic(DA) tech. | lab12 document |
| Lab 13 | matrix inner product using Systolic array | lab13 document |
| Lab 14 | Cordic Design | lab14 document |
| Project1 | 21-tap fir filter design (direcr/Symmetric form with pipeline tech.) | project1 document |
| Final Project | 1D 8-point DCT (using cordic, DA tech.) | final project document |