Library and Example code for use of the Jefferson Lab VME Based 250MHz Flash ADC 250 V3 Module

Requires: FADC V3

• Linux >=2.6.18
  • GE kernel module with jvme library

LINUX library and readout lists:

libfaV3.so	Shared Library object for std FADC Lib
rol/fav3_list.c	CODA Readout list for 1 FADC
rol/fav3_vxs_list.c	CODA Readout list for multiple FADC in a VXS crate

Source files and headers:

faV3Lib.{c,h}	Library
faV3Itrig.c	Library extensions for Internal trigger
faV3FirmwareTools.c	Library extensions for firmware updates
faV3Config.{c,h}	Library extensions for configuration files

Programs:

firmware/faV3FirmwareUpdate	Program to update firmware for a single FADC
firmware/faV3GFirmwareUpdate	Program to update firmware for an entire crate of FADC
test/faV3GStatus	Show the status of all FADC in crate
test/faV3GReloadFpga	Reload FPGA for all FADC in crate
test/faV3ReloadFpga	Reload FPGA for FADC at specified address

Basics:

faV3Init(addr, addr_inc, num, iFlag)

• addr: A24 VME address set by micro switches on the FADC. (using slot convention: slotnumber << 19)
• addr_inc: With multiple boards this is the value that the A24 address is incremented between the base addresses of each board (using slot convention: 1 << 19 = 0x080000)
• num: Number of FADCs to initialize
• iFlag: 16 bit integer
  • Low 6 bits - Specifies the default Signal distribution (clock,trigger) sources for the board (INTernal, FrontPanel, VXS, VME(Soft))
    • bit 0: defines Sync Reset source 0 : FAV3_INIT_SOFT_SYNCRESET VME (Software Sync-Reset) 1 : FAV3_INIT_EXT_SYNCRESET Front Panel/VXS/P2 (Depends on Clk/Trig source selection)
    • bits 3-1: defines Trigger source 0 0 0 : FAV3_INIT_SOFT_TRIG VME (Software Triggers) 0 0 1 : FAV3_INIT_FP_TRIG Front Panel Input 0 1 0 : FAV3_INIT_VXS_TRIG VXS (P0) 1 0 0 Internal Trigger Logic (HITSUM FPGA) (all others Undefined - default to Internal)
    • bits 5-4: defines Clock Source 0 0 : FAV3_INIT_INT_CLKSRC Internal 250MHz Clock 0 1 : FAV3_INIT_FP_CLKSRC Front Panel 1 0 : FAV3_INIT_VXS_CLKSRC VXS (P0) 1 1 : FAV3_INIT_P2_CLKSRC P2 Connector (Blackplane)

• High 10bits - A16 Base address of FADC Signal Distribution Module This board can control up to 7 faV3 Boards. Clock Source must be set to Front Panel (bit4 = 1)
• bit 16: FAV3_INIT_SKIP Exit before board initialization
• bit 17: FAV3_INIT_USE_ADDRLIST

Initialize modules using contents of array faV3AddrList[] with num as the number of elements to use. For example

extern uint32_t faV3AddrList[FAV3_MAX_BOARDS];
faV3AddrList[0] = 0xed0000;
faV3AddrList[1] = 0xee0000;
faV3AddrList[2] = 0xef0000;
faInit(faV3AddrList[0], 0, 3, FAV3_INIT_USE_ADDRLIST);

• bit 18: FAV3_INIT_SKIP_FIRMWARE_CHECK

Initialize faV3 modules even if their firmware version is not supported by the library (useful for firmware update programs and debugging).

• bit 19: FAV3_INIT_MULTIBLOCK_ONLY

Initialize faV3 modules without configuration of A32 address for individual readout. Multi-board readout using token passing will still be configured.

• bit 20: FAV3_INIT_VXS_READOUT_ONLY

Initialize faV3 modules without any configuration of A32 address for readout. Multi-board readout using VXS to VTP will be configured

• bit 21: FAV3_INIT_A32_SLOTNUMBER

Initialize faV3 modules using slot number to determine A32 address for individual and token passing readout. Programmed I/O readout will not work with this configuration (DMA Only). Individual A32 addresses will be configured with slotnumber << 23 and multi-board A32 address set to 22 << 23:

Slot	A32
3	0x0180 0000
4	0x0200 0000
5	0x0280 0000
…	…
20	0x0A00 0000
MB	0x0B00 0000

Common Modes of Operation:

iFlag	CLK	TRIG	SYNC	description
0x0	Int	Soft	Soft	Debug/Test
0x2	Int	FP	Soft	Single Board
0x3	Int	FP	FP	Single Board
0x10	FP	Soft	Soft	VME SDC, Debug/Test
0x13	FP	FP	FP	VME SDC
0x20	VXS	Soft	Soft	VXS SD, Debug/Test
0x25	VXS	VXS	VXS	VXS SD

Example:

Initialize a single FADC at address 0xed0000 in Debug/Test mode (Internal Clock, Front Panel Trigger).

faV3Init(0xed0000, 0x0, 1, 0x0);

Example

Initialize 5 FADC boards at using slot convention for slots 3 - 7 Address = (slot << 19)

Slot	Address
3	0x180000
4	0x200000
5	0x280000
6	0x300000
7	0x380000

FADC SDC Board at 0xed00 Front Panel Trigger, Sync, and Clock

faV3Init(0x180000, 0x080000, 5, 0xed13);

or

faV3Init(3 << 19, 1 << 19, 5, 0xed13);

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