- lab1: Implement a MIPS instruction simulation platform based on c language
- lab2: Realized the joint optimization of cache prefetching and replacement strategies, and used the champsim based simulator to conduct experiments to explore the impact of the unified memory access mode on the joint prefetching and replacement strategies. The experimental model improved the performance of simple optimal policy combinations
- lab3: Implement a multi cycle cpu based on verilog language, from Loongson company
- lab4: Implement a pipeline cpu based on verilog language, realized branch prediction and data forwarding bypass optimization, from Loongson company
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Course assignments at Nankai University.Realized the joint optimization of cache prefetching and replacement strategies, and used the Champsim simulator to conduct experiments to explore the impact of the unified memory access mode on the joint prefetching and replacement strategies.
JensenWei007/Computer-Architecture
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Course assignments at Nankai University.Realized the joint optimization of cache prefetching and replacement strategies, and used the Champsim simulator to conduct experiments to explore the impact of the unified memory access mode on the joint prefetching and replacement strategies.
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