Improved UVM APB RAL: functional coverage, protocol compliance, assertions, and error signalling

[jissjoseph1997]

UVM APB RAL Design Enhancements:

• Designed an APB slave module for a traffic control system with an FSM managing transaction phases (idle, setup, access, transfer).
• Incorporated APB-compliant signaling (pready, pslverr) for error handling and transaction management.

Functional Enhancements:

• Added error signaling for invalid address access to enhance design robustness.
• Modeled control, status, and timer registers within RAL, simplifying verification.
• Implemented RAL-based read, write, and reset functionalities in the testbench.

Functional Coverage:

• Added coverage constructs for mod_en, bl_yellow, and bl_red fields, including reset values.
• Enabled detailed coverage collection and database generation.

Verification Enhancements:

• Developed sequences for valid and invalid address scenarios, ensuring thorough verification.
• Added assertions to validate pslverr signaling for invalid addresses.
• Enhanced debug information with systematic tasks in testbench components.
• Integrated invalid_address_test to verify DUT behavior under error conditions.

Top-Level Updates:

• Updated the top module with additional APB signals and reset handling.
• Added coverage database saving and reset value checks.

Debugging and Reporting:

• Improved observability with detailed logs, assertions, and reset sequence checks for seamless debugging.

[devdi4522]

Is it possible to run this using Opentitan? If so, how do I go about doing it?