Computer Engineer | Embedded Systems | FPGA Design | Machine Learning

📫 [email protected]  |  LinkedIn  |  GitHub

I'm a Computer Engineer, Research Assistant, and current Master’s student in Electrical Engineering at UTRGV. I blend hardware design and machine learning to solve real-world challenges, thriving at the intersection of embedded systems, FPGAs, and intelligent computation.

From simulating custom RISC pipelines to designing real-time DSP systems for audio enhancement, I focus on building efficient, impactful systems that bridge theory and application.

I believe in engineering for impact — building systems that are fast, intelligent, and meaningful.

Designed a custom 24-bit RISC CPU with a five-stage pipeline and a cycle-accurate simulator in Python. The project includes a custom ISA, full register and memory tracing, and pipeline execution logs. Now expanding into a full Verilog RISC-V implementation targeting the DE1-SoC board.

Building a low-latency, real-time audio enhancement system tailored for trumpet players, powered by the DE1-SoC FPGA. Combines HPS-based pitch detection with FPGA-accelerated DSP (e.g., pitch correction, noise gating, and reverb), targeting <15ms latency for live performance use.

A 12-state Moore machine implemented in Verilog and deployed on the Nexys A7-100T FPGA. The system tests button press sequences and provides visual feedback using LEDs, showcasing finite state machine design, modular HDL, and hardware debugging.

Developed a network-based control interface for DE1-SoC LEDs using TCP/IP. Features a client-server architecture, where commands from a remote device control hardware via HPS–FPGA integration. Demonstrates embedded Linux, socket programming, and real-time interfacing.

A collection of CMOS digital circuits including XOR gates, adders, and an 8-bit ripple-carry adder, designed and simulated using Cadence Virtuoso. Each includes schematic, layout, simulation waveforms, and successful LVS checks — showcasing hands-on transistor-level design.

🧪 Research Assistant @ UTRGV (2025–Present)
Developing fast, scalable federated Gaussian process models (F-IGP) with 1K+ update cycles, achieving strong accuracy and runtime gains in decentralized multi-agent simulations.

🧬 Undergraduate Researcher @ UTRGV (2024)
Built a real-time facial recognition system using a custom CNN to measure attentiveness in classrooms (90%+ accuracy).

🚗 CREST MECIS Fellow (2023)
Developed ML models to reduce autonomous vehicle conflict zones by 50%, focusing on real-time decision-making.