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JuanCantu1/README.md

Hi, I'm Juan Cantu ๐Ÿ‘‹

Computer Engineer | Embedded Systems | FPGA Design | Machine Learning

๐Ÿ“ซ [email protected] ย |ย  LinkedIn ย |ย  GitHub


๐Ÿ“Œ Who I Am

I'm a Computer Engineer, Research Assistant, and current Masterโ€™s student in Electrical Engineering at UTRGV. I blend hardware design and machine learning to solve real-world challenges, thriving at the intersection of embedded systems, FPGAs, and intelligent computation.

From simulating custom RISC pipelines to designing real-time DSP systems for audio enhancement, I focus on building efficient, impactful systems that bridge theory and application.

I believe in engineering for impact โ€” building systems that are fast, intelligent, and meaningful.


๐Ÿš€ Featured Projects

๐Ÿ–ฅ๏ธ RISC-V CPU Design (In Progress)

Designed a custom 24-bit RISC CPU with a five-stage pipeline and a cycle-accurate simulator in Python. The project includes a custom ISA, full register and memory tracing, and pipeline execution logs. Now expanding into a full Verilog RISC-V implementation targeting the DE1-SoC board.


Building a low-latency, real-time audio enhancement system tailored for trumpet players, powered by the DE1-SoC FPGA. Combines HPS-based pitch detection with FPGA-accelerated DSP (e.g., pitch correction, noise gating, and reverb), targeting <15ms latency for live performance use.


A 12-state Moore machine implemented in Verilog and deployed on the Nexys A7-100T FPGA. The system tests button press sequences and provides visual feedback using LEDs, showcasing finite state machine design, modular HDL, and hardware debugging.


Developed a network-based control interface for DE1-SoC LEDs using TCP/IP. Features a client-server architecture, where commands from a remote device control hardware via HPSโ€“FPGA integration. Demonstrates embedded Linux, socket programming, and real-time interfacing.


A collection of CMOS digital circuits including XOR gates, adders, and an 8-bit ripple-carry adder, designed and simulated using Cadence Virtuoso. Each includes schematic, layout, simulation waveforms, and successful LVS checks โ€” showcasing hands-on transistor-level design.


๐Ÿ”ง Core Skills

๐Ÿ“ Languages

C C++ Python Verilog MATLAB Java


๐Ÿ”Œ Hardware Design & Embedded Systems

FPGA SystemVerilog Arduino Raspberry Pi


๐Ÿง  Machine Learning & Scientific Tools

PyTorch TensorFlow Keras Scikit-Learn OpenCV NumPy Pandas


๐Ÿงฐ Tools for Development & Design

Vivado Quartus Cadence Git Docker Linux


๐Ÿ“š Experience Highlights

๐Ÿงช Research Assistant @ UTRGV (2025โ€“Present)
Developing fast, scalable federated Gaussian process models (F-IGP) with 1K+ update cycles, achieving strong accuracy and runtime gains in decentralized multi-agent simulations.

๐Ÿงฌ Undergraduate Researcher @ UTRGV (2024)
Built a real-time facial recognition system using a custom CNN to measure attentiveness in classrooms (90%+ accuracy).

๐Ÿš— CREST MECIS Fellow (2023)
Developed ML models to reduce autonomous vehicle conflict zones by 50%, focusing on real-time decision-making.


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  1. DSP-System-for-Trumpet-Audio-Enhancement DSP-System-for-Trumpet-Audio-Enhancement Public

    Real-time trumpet audio enhancement system with note detection, frequency analysis, and live DSP effects implemented across the DE1-SoCโ€™s ARM processor and Cyclone V FPGA.

    2

  2. CPU-Design CPU-Design Public

    Python-based simulator for a 24-bit RISC processor with a five-stage pipeline. Focused on instruction-level, cycle-accurate modeling.

    SystemVerilog 2

  3. Interactive-Memory-Game Interactive-Memory-Game Public

    Interactive memory game implemented in Verilog and deployed on Nexys-A7 FPGA using FSM-based logic.

    Verilog 2

  4. Network-Controlled-LED-System Network-Controlled-LED-System Public

    Network-Controlled LED system on DE1-SoC using TCP/IP, ARM-HPS, and FPGA-based LED control.

    2

  5. VLSI-Projects VLSI-Projects Public

    CMOS digital circuits implemented at the transistor level with schematic, layout, waveform simulation, and LVS verification, from basic logic gates to an 8-bit ripple-carry adder.

    2

  6. DraftMaster DraftMaster Public

    Python 2