Skip to content

Commit d1208ae

Browse files
authored
Merge pull request #86 from avi-jois/sync_stage_delay_fix
Use assignment delay parameter in SyncStage
2 parents 64c3009 + 6161ce2 commit d1208ae

1 file changed

Lines changed: 4 additions & 2 deletions

File tree

src/ordt/output/systemverilog/common/wrap/WrapperRemapSyncStagesXform.java

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@
44
import java.util.HashMap;
55
import java.util.List;
66

7+
import ordt.parameters.ExtParameters;
8+
79
public class WrapperRemapSyncStagesXform extends WrapperRemapXform {
810

911
protected int delayStages = 1;
@@ -52,8 +54,8 @@ public List<String> getXformModuleDef() {
5254
outList.add(" always @ (*)");
5355
outList.add(" dly[0] = in_sig;");
5456
outList.add(" always @ (posedge clk) begin");
55-
outList.add(" for (idx = 1; idx <= STAGES; idx=idx+1)");
56-
outList.add(" dly[idx] <= #1 dly[idx-1];");
57+
outList.add(" for (idx = 1; idx <= STAGES; idx++)");
58+
outList.add(" dly[idx] <= " + ExtParameters.sysVerSequentialAssignDelayString() + "dly[idx-1];");
5759
outList.add(" end");
5860
outList.add(" assign out_sig = dly[STAGES];");
5961
outList.add("endmodule");

0 commit comments

Comments
 (0)