moore_fsm_verilog/fsm.v at main · KnightRider-hash/moore_fsm_verilog · GitHub

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17.01.2026 18:41:44
// Design Name:
// Module Name: fsm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module fsm();
reg D;
 reg Clk,Rst;
 wire O;
 moore_fsm dut(.data(D),.rst(Rst),.clk(Clk),.out(O));
 initial begin
 Clk=0;
 D=0; Rst=0;
 @(posedge Clk) Rst=1;
 @(posedge Clk) Rst=0; D=1;
 @(posedge Clk) D=1;
 @(posedge Clk) D=0;
 @(posedge Clk) D=1;
 @(posedge Clk) D=1;
 @(posedge Clk) D=0;
 @(posedge Clk) D=0;
 @(posedge Clk) D=1;
 @(posedge Clk) D=0;
 @(posedge Clk) D=1;
 @( posedge Clk) Rst=1;
 $stop;
 end
 always #5 Clk=~Clk;
endmodule