Moore_Finite_State_Machine

This project implements a Moore Finite State Machine (FSM) in Verilog HDL for serial sequence detection. The output is asserted only in a specific state, ensuring stable Moore-type behavior. The design uses a two-process FSM structure and supports overlapping sequences.

Port Description

Signal	Direction	Description
clk	Input	System clock (posedge)
rst	Input	Active-high reset
data	Input	Serial input bit
out	Output	Asserted when target state is reached

State Encoding

State	Binary	Meaning
S0	00	Initial / Idle
S1	01	Detected 1
S2	10	Detected 10
S3	11	Sequence detected (output = 1)

Output Logic

State	out
00	0
01	0
10	0
11	1

Reset Behavior

Condition	State	Output
rst = 1	00	0
rst = 0	Normal operation	State-dependent