moore_fsm_verilog/moore_mach.v at main · KnightRider-hash/moore_fsm_verilog · GitHub

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17.01.2026 13:56:41
// Design Name:
// Module Name: moore_mach
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module moore_fsm(
    input data,
    input clk,
    input rst,
    output reg out
    );
    reg [1:0] state, next;

// State register
always @(posedge clk or posedge rst) begin
    if (rst)
        state <= 2'b00;
    else
        state <= next;
end

// Next state & output logic
always @(*) begin
 next=state;
    case (state)
        2'b00: begin
            if (data)
                next = 2'b01;
            else
                next = 2'b00;
        end

        2'b01: begin
            if (data)
                next = 2'b01;
            else
                next = 2'b10;
        end

        2'b10: begin
            if (data)
                next = 2'b11;
            else
                next = 2'b00;
        end
     2'b11:begin
                if(data)
                   next=2'b01;
                else
                     next=2'b00;
         end
        default: begin
            next = 2'b00;
        end
    endcase
end
always@(*)begin
if(state==2'b11)
    out=1'b1;
else
    out=1'b0;
end

endmodule