mips-5-stage-pipeline

5-stage pipeline based on mips. implemented using verilog

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
lab6.cache/wt		lab6.cache/wt
lab6.hw		lab6.hw
lab6.ip_user_files		lab6.ip_user_files
lab6.sim/sim_1/behav/xsim		lab6.sim/sim_1/behav/xsim
lab6.srcs		lab6.srcs
1.png		1.png
Instruction		Instruction
README.md		README.md
data		data
lab6.xpr		lab6.xpr

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