WIP: Refactor DTR+RI UART handler#1
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| gpio_pin_set_dt(&get_dev_config(get_dev(data))->ri_gpio, 1); | |
| gpio_pin_set_dt(&get_dev_config(get_dev(data))->ri_gpio, 0); |
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Is there an actual reason for not using nrf_gpio_cfg_sense_set?
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We have to use level triggered interrupts to achieve < 4uA sleeps.
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When would this be utilized? With AT#XSLEEP?
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Work in progress: Not ready. * Refactor to use just Zephyr GPIO API * Use Devicetree to define pins * Refactor DTR UP/DOWN events to ASSERT/DEASSERT * Logic level 1 is asserted, use DT to change 0/1 level of that. * Remove support of DTE device, that is separate driver TODO: * sw_dtr should not keep RX buffers. Instead when RX is enabled, feed buffer to UART from application call. * When buffer is needed, make a callback to app to request a buffer. * When UART is powered down because of DTR, block RX_STOP and RX_DISABLE events going to application, so app thinks the UART keeps on going. Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
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TODO: Not ready.