In this RTL design project, an AI accelerator for MNSIT digit is deployed with these features:

1. 4 Neural layers with pruning weights and biases for all neurons.
2. AXi-4 Protocol for data transfer is employed.
3. Taped out the semicustom design from Efabless with OpenLane.
4. The design has been validated on Zedboard.

Layout, LEF, Synthesized verilogs are here: https://github.com/MdOmarFaruque/HW_V1/tree/main/user_project_wrapper/runs/24_08_21_21_23/results/final

Feel free to reach out if you have any questions at mdomorfaruque007@gmail.com