[https://nvbugs/5575920][fix] Fix cublas/cublasLt handle creation memory not sufficient error #8881
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Signed-off-by: Wangshanshan <[email protected]>
…uce max tokens in kv cache config. Signed-off-by: Wangshanshan <[email protected]>
…uce memory fraction in kv cache config. Signed-off-by: Wangshanshan <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
Signed-off-by: Wangshanshan <[email protected]>
📝 WalkthroughWalkthroughAdds memory instrumentation and robust error handling to CUDA cuBLAS/CUBLAS LT handle creation and destruction in opUtils.cpp, capturing memory state and logging on failure. Updates three fp8kv test cases to include Changes
Estimated code review effort🎯 2 (Simple) | ⏱️ ~10–15 minutes
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✅ Passed checks (1 passed)
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🧹 Nitpick comments (1)
cpp/tensorrt_llm/common/opUtils.cpp (1)
255-261: Consider CamelCase for struct members (optional).While the current snake_case naming (
free_mb,total_mb,free_percent) is readable, TRT-LLM coding guidelines prefer CamelCase (e.g.,freeMb,totalMb,freePercent) for consistency. Since this is an internal POD struct, the readability trade-off is acceptable.As per coding guidelines
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cpp/tensorrt_llm/common/opUtils.cpp(2 hunks)tests/integration/defs/accuracy/test_llm_api_pytorch.py(2 hunks)
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**/*.{h,hpp,hh,hxx,cpp,cxx,cc,cu,cuh}
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cpp/tensorrt_llm/common/opUtils.cpp
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cpp/tensorrt_llm/common/opUtils.cpptests/integration/defs/accuracy/test_llm_api_pytorch.py
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🧠 Learnings (7)
📓 Common learnings
Learnt from: venkywonka
Repo: NVIDIA/TensorRT-LLM PR: 6029
File: .github/pull_request_template.md:45-53
Timestamp: 2025-08-27T17:50:13.264Z
Learning: For PR templates in TensorRT-LLM, avoid suggesting changes that would increase developer overhead, such as converting plain bullets to mandatory checkboxes. The team prefers guidance-style bullets that don't require explicit interaction to reduce friction in the PR creation process.
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/multimem.h:20-30
Timestamp: 2025-09-23T15:13:48.819Z
Learning: TRT-LLM targets modern CUDA toolkits that support FP8 datatypes, so cuda_fp8.h can be included unconditionally without version guards in TRT-LLM code.
📚 Learning: 2025-09-23T15:13:48.819Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/multimem.h:20-30
Timestamp: 2025-09-23T15:13:48.819Z
Learning: TRT-LLM targets modern CUDA toolkits that support FP8 datatypes, so cuda_fp8.h can be included unconditionally without version guards in TRT-LLM code.
Applied to files:
cpp/tensorrt_llm/common/opUtils.cpp
📚 Learning: 2025-08-25T00:03:39.294Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 7104
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1185-1189
Timestamp: 2025-08-25T00:03:39.294Z
Learning: TLLM_CHECK_WITH_INFO is a host-side utility function and cannot be called from CUDA device functions (those marked with __device__ or __global__). In device code, assert() is the primary mechanism for handling "should never happen" conditions, and like standard C++ assert, CUDA's assert only works in debug builds and is compiled out in release builds.
Applied to files:
cpp/tensorrt_llm/common/opUtils.cpp
📚 Learning: 2025-08-14T21:04:50.248Z
Learnt from: thorjohnsen
Repo: NVIDIA/TensorRT-LLM PR: 6910
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:0-0
Timestamp: 2025-08-14T21:04:50.248Z
Learning: In KV cache onboarding logic during prefill in cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp, when calculating which blocks fall within the attention window, use getTokensPerBlock() to advance token indices rather than block->getUniqueTokens().size(), because the calculation needs to consider the post-prefill state where blocks will be filled to capacity, not their current token count.
Applied to files:
tests/integration/defs/accuracy/test_llm_api_pytorch.py
📚 Learning: 2025-08-26T09:37:10.463Z
Learnt from: jiaganc
Repo: NVIDIA/TensorRT-LLM PR: 7031
File: tensorrt_llm/bench/dataclasses/configuration.py:90-104
Timestamp: 2025-08-26T09:37:10.463Z
Learning: In TensorRT-LLM's bench configuration, the `get_pytorch_perf_config()` method returns `self.pytorch_config` which is a Dict[str, Any] that can contain default values including `cuda_graph_config`, making the fallback `llm_args["cuda_graph_config"]` safe to use.
Applied to files:
tests/integration/defs/accuracy/test_llm_api_pytorch.py
📚 Learning: 2025-08-26T09:37:10.463Z
Learnt from: jiaganc
Repo: NVIDIA/TensorRT-LLM PR: 7031
File: tensorrt_llm/bench/dataclasses/configuration.py:90-104
Timestamp: 2025-08-26T09:37:10.463Z
Learning: In TensorRT-LLM, the `get_pytorch_perf_config()` method returns `self.pytorch_config` which can contain default `cuda_graph_config` values, so `llm_args` may already have this config before the extra options processing.
Applied to files:
tests/integration/defs/accuracy/test_llm_api_pytorch.py
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation.
Applied to files:
tests/integration/defs/accuracy/test_llm_api_pytorch.py
🧬 Code graph analysis (1)
tests/integration/defs/accuracy/test_llm_api_pytorch.py (1)
tensorrt_llm/llmapi/llm_args.py (1)
KvCacheConfig(976-1110)
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🔇 Additional comments (7)
tests/integration/defs/accuracy/test_llm_api_pytorch.py (2)
158-162: LGTM: Appropriate memory mitigation for FP8 KV cache tests.The reduced memory fraction (0.8 instead of default ~0.9) provides headroom for cuBLAS handle allocation when using FP8 KV cache. This aligns with the enhanced memory diagnostics added in cpp/tensorrt_llm/common/opUtils.cpp.
196-200: LGTM: Consistent memory configuration for multi-GPU FP8 tests.The same memory fraction adjustment is consistently applied to the multi-GPU variant, maintaining uniformity across the FP8 test suite.
cpp/tensorrt_llm/common/opUtils.cpp (5)
264-274: LGTM: Robust memory info retrieval.The function correctly handles edge cases (zero total memory) and provides clear, human-readable memory statistics in MB and percentages.
277-293: LGTM: Excellent diagnostic and error reporting helpers.Both functions provide valuable diagnostics:
logMemoryUsage()enables tracing of memory state at handle creation timethrowCublasErrorWithMemInfo()delivers actionable error messages with concrete memory statistics and mitigation adviceThe suggestion to reduce
free_gpu_memory_fractiondirectly guides users toward the same solution applied in the test changes.
302-311: LGTM: Enhanced cuBLAS handle creation with memory diagnostics.The additions provide valuable diagnostic context:
- Memory state is logged before handle creation, enabling correlation with failures
- Error messages include memory statistics and actionable guidance
- The pattern is consistent and maintainable
317-321: LGTM: Safer error handling on handle destruction.Replacing assertion with warning logging is a robust improvement. Handle destruction typically occurs during shutdown, where assertions can cause ungraceful termination. The logged status code still provides diagnostic information while allowing cleanup to continue.
333-352: LGTM: Consistent instrumentation for cuBLAS LT handles.The changes mirror those in
getCublasHandle(), ensuring uniform diagnostic coverage and error handling across both cuBLAS and cuBLAS LT handle lifecycle events. The consistency improves maintainability.
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