Add support for MSR/MRS (banked register) for 32-bit ARM architectures

[jonathanzetier]

This adds support for the MRS/MSR (banked register) 32-bit ARM instructions. Documentation for these instructions can be found here:

https://developer.arm.com/documentation/ddi0597/2024-12/Base-Instructions/MRS--Banked-register---Move-Banked-or-Special-register-to-general-purpose-register-

https://developer.arm.com/documentation/ddi0597/2024-12/Base-Instructions/MSR--Banked-register---Move-general-purpose-register-to-Banked-or-Special-register-

I wanted to be able to map SYSm values directly to registers, and then be able to map instruction fields to SYSm values; however, SYSm isn't a contiguous bitfield (or even in the same 16-bit chunk for thumb instructions), which seems to limit my options. Please let me know if there's a cleaner approach than the one I ended up using for this. I also wasn't sure how many .pspec files to add the new volatile register section to, so I just did the two that seemed to be used for the architectures that these instructions are present in (v7 and v8).

I'm attaching some files that can help with testing, package.zip, which include:

• Dumb test binaries that iterate through the encoding space of these instructions (arm.bin, thumb.bin)
• The script used to generate them (generate.py)
• What objdump thinks they should disassemble to (arm.objdump, thumb.objdump); the commands used to generate these are commentsin the generate.py script.

I didn't automatically analyze the binaries, I just opened them as raw images and manually disassembled from the start with their corresponding architecture (thumb for thumb.bin, arm for arm.bin).