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Awesome EDA 🛠️

A curated list of high-quality Electronic Design Automation (EDA) tools, projects, tutorials, books, and resources.

This list focuses on actively maintained, open-source, production-ready, or education-focused EDA tools for PCB, FPGA, ASIC, and VLSI design — excellent for learning, hobby projects, or real silicon tape-outs in 2026.


Contents

Getting Started

Books

Hands-on Tutorials & Example Flows

Open-Source EDA Tools & Flows


PCB & Schematic Design

Tool Description Year Initialized
KiCad professional-grade schematic capture + PCB layout (industry standard open alternative)
LibrePCB modern, intuitive EDA suite with excellent library management
eSim full-stack circuit design, simulation, and PCB (KiCad + ngspice + Verilator)

HDL Simulation & Verification

Tool Description Year Initialized
Verilator fastest Verilog/SystemVerilog simulator (used in industry)
Icarus Verilog lightweight Verilog simulator & synthesizer
GHDL VHDL simulator with excellent IEEE support
sv2v SystemVerilog to Verilog translator widely used in FPGA flows 2019

Logic Synthesis & FPGA Tools

Tool Description Year Initialized
Yosys extensible Verilog RTL synthesis suite 2012
Berkeley-ABC industrial-strength logic synthesis and verification system 2005
nextpnr FPGA place-and-route (Lattice, ECP5, iCE40, etc.)
VTR (Verilog-to-Routing) academic FPGA CAD flow 2012

ASIC & Physical Design Flows

Tool Description Year Initialized
OpenROAD autonomous RTL-to-GDSII flow
OpenLane complete automated ASIC flow (used for real tape-outs)
iEDA full netlist-to-GDS infrastructure
OpenSTA static timing analysis engine used in modern open ASIC flows 2018
RePlAce analytic global placement engine 2018
TritonCTS clock tree synthesis engine 2018
OpenDP detailed placement optimizer 2018
OpenTimer high-performance timing analysis framework 2015

Layout Editors & Viewers

Tool Description Year Initialized
Magic VLSI venerable interactive layout editor 2017
KLayout powerful GDS/OASIS viewer, editor, and DRC tool 2017
Qrouter grid-based autorouter for IC layouts 2013

Analog & Mixed-Signal Tools

Tool Description Year Initialized
ngspice SPICE circuit simulator (industry-grade open source) 1999
Xschem schematic capture for analog/mixed-signal
ALIGN automated analog layout synthesis framework 2018

Tools & Utilities

Tool Description Year Initialized
SkyWater 130nm PDK free manufacturable process design kit
Open_PDKs open-source process design kits
CVC circuit verifier 2009
Netgen LVS (Layout vs Schematic)

Experimental, Research & Specialized EDA Projects (From clin99 Awesome-EDA See also: https://github.com/clin99/awesome-eda)

Tool Primary Area Description Year Initialized
PyMTL Hardware Modeling Python-based hardware modeling and simulation framework used in academia 2012
ILAng SoC Verification Instruction-Level Abstraction modeling and verification platform 2016
Galois Parallel Framework CAD Infrastructure Parallel algorithm research framework used in EDA experimentation 2010
HAMMER Flow Orchestration Modular ASIC flow generation and configuration framework 2017
Lgraph Synthesis Infrastructure Graph-based synthesis and simulation infrastructure 2018
MAGICAL Analog Layout Automation Machine-generated analog IC layout automation framework 2019
AMPSE Analog Design Automation Analog parameter search and optimization engine 2019
Analog Known Good Designs Analog Reference Designs Verified analog circuit design repository 2019
Circuit IP Sanitizer Analog Verification IP validation and sanitization tooling 2019
AMC (Async Memory Compiler) Memory Design Asynchronous memory compiler research project 2019
PVT Sensors Analog Test Infrastructure Open PVT sensor development framework 2019
UW IDEA Analog TestCases Analog Benchmarks Analog testing and validation circuits 2019
OpenPiton Research SoC Platform Manycore open research processor platform 2018
PRGA FPGA Workflow Research FPGA architecture exploration workflow 2018
OpenFPGA (FPGA-SPICE) FPGA Modeling FPGA architecture modeling and SPICE co-simulation 2018
EPFL Logic Benchmark Suite Benchmarks Widely used combinational logic synthesis benchmarks 2018
Parser-SPEF Physical Design Utility SPEF parasitic extraction file parser 2018
UW BSG Pipecleaner Suite Verification Benchmarks Microarchitecture testing framework 2019
Graywolf Placement Academic ASIC placement research tool 2014
BoxRouter Routing Global routing academic prototype 2016

Community & Learning Resources

Contributing

Contributions are highly welcome! Please read the rules below.

Rules:

  • Only high-quality, actively maintained tools (recent commits, good documentation, real usage).
  • One line per entry:
    - [Tool Name](link) – Short, compelling one-sentence description.

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