Nuclei Microcontroller Software Interface Standard V1.6.0

Caution

Please use Nuclei RISC-V Toolchain >= Nuclei RISC-V Toolchain 2025.10

Breaking Changes

• 32-bit AMO Intrinsic APIs Reimplemented: The 32-bit AMO intrinsic APIs in core_feature_base.h (__AMOADD_W, __AMOAND_W, __AMOOR_W, __AMOXOR_W, __AMOMAXU_W, __AMOMAX_W, __AMOMINU_W, __AMOMIN_W, __AMOSWAP_W, __CAS_W) have been completely reimplemented. The previous implementation had concurrency issues (returning memory value instead of the result register) and incorrect instruction suffixes (.d instead of .w), which did not conform to the RISC-V intrinsic API semantics. Users relying on the old behavior should review and update their code accordingly.
• RVV Macro Renamed: The RISCV_MATH_VECTOR_FLOAT16 macro in riscv_math_types_f16.h has been renamed to RISCV_MATH_VECTOR_ZVFH. Users who directly referenced the old macro name will need to update their code.
• Fine-Grained RVV Macros: The single RISCV_MATH_VECTOR macro has been replaced by more fine-grained capability macros (RISCV_MATH_VECTOR_ZVFH, RISCV_MATH_VECTOR_ZVE32X, RISCV_MATH_VECTOR_ZVE32F, RISCV_MATH_VECTOR_ZVE64X, RISCV_MATH_VECTOR_ZVE64F, RISCV_MATH_VECTOR_ZVE64D), which are derived from compiler predefined macros based on the --march option. All DSP and NN source files have been adapted accordingly.
• VPU Agnostic Change: RVV Intrinsic APIs have been updated to adapt to the VPU agnostic feature. Pay attention to cases where tail elements and non-mask elements are used in RVV calculation.

Highlights

• DSP RVV Optimization Expansion: Added RVV optimization for fast functions, including ComplexMathFunctions, FilteringFunctions, and MatrixFunctions.
• DSP/NN Fine-Grained Macro Adaptation: All DSP (~325 files) and NN (~56 files) source files have been adapted to use the appropriate fine-grained RVV macros, ensuring each function only compiles RVV code for the minimum required vector extension.
• NMSIS-Core Enhancements:
  • Added precise ECC injection support with IINFO_ECC_INJ_WAY_Type union, IINFO_IsPreciseECCInjSupported() and IINFO_SetPreciseECCInjWay() APIs.
  • Extended SMPCC with new register types (CC_INV_RANGE_Type, CC_ECC_INJ_WAY_Type, CC_ECC_INJ_ADDR_Type, CC_ECC_INJ_DATA_Type, IOCP_ATTR_RMP_Type), new SMPCC_ClearBusErrPending() API, and updated error inject functions to support precise ECC injection.
  • Added __ECLIC_VER macro with default value of 1 for ECLIC version identification.

Bug Fixes

• NMSIS-Core:
  • Fixed __ECLIC_SetModeIRQ using wrong register (ECLIC->SCTRL corrected to ECLIC->CTRL).
  • Fixed MFlushCCache, SFlushCCache, and UFlushCCache not clearing pending error status (RESC/FESC/BESC) before issuing Cluster Cache commands.
  • Fixed DisableSUCCM using incorrect _VAL2FLD approach, replaced with direct bitmask clearing.
  • Fixed ECC_IsTLBSupportECC removing incorrect PLIC dependency, now directly checks mtlbcfginfo.b.ecc.
  • Fixed ECC_IsTLBSingleBitErrorOccured and ECC_IsTLBDoubleBitErrorOccured using wrong RAMID mask (DLM instead of TLB).
  • Fixed __CTZ in core_compatiable.h missing boundary check, which could cause an infinite loop when input is 0. Now returns __RISCV_XLEN for zero input.
  • Fixed PLIC_SetThreshold macro signature (removed incorrect source parameter) and PLIC_CompleteContextInterrupt parameter description in core_feature_plic.h.
  • Fixed ssnpm field comment incorrectly referencing Smnpm extension instead of Ssnpm in core_feature_iinfo.h.
  • Fixed multiple typos in CSR field comments and ECC-related descriptions.
  • Fixed MLockDCacheLine replaced with __LW + __RWMB in DCache ECC injection functions in core_feature_ecc.h.
  • Fixed ECC_IsTLBSupportECC to remove incorrect PLIC dependency in core_feature_ecc.h.

For detailed information, please refer to the NMSIS online documentation.

Full Changelog: 1.5.0...1.6.0