Low-Level Systems & Performance Engineering

University of Waterloo — Computer Science & Math

I spend my time in the space between hardware and software — kernels, instruction pipelines, cache behavior, concurrency primitives. I like problems where correctness alone isn't the bar and the clock matters. Open to full-time systems / low-latency engineering roles.

Real-Time OS Kernel — C · Assembly Microkernel built from scratch: custom context switching, message-passing IPC, interrupt handlers, and kernel/user-space separation for precise real-time timing control.

ML Kernel Optimization on RISC-V — C · RISC-V Assembly Hand-optimized a BatchNorm kernel with SIMD/vector processing — 96.2% FPU utilization, 7.46× speedup. DMA tiling and double-buffering cut data movement overhead to under 3.6%.

• Codeforces: Master, rating 2136
• ICPC North Central NA Regional: 13th Place

Internships in systems and infrastructure engineering at large-scale consumer and AI platforms — mobile performance/concurrency, distributed caching, and high-throughput data infrastructure. Specifics available on request.

Concepts: OS internals (kernel/user space, scheduling, memory management, IPC) · low-latency systems (cache locality, concurrency, perf profiling) · NUMA fundamentals · storage engines (B+ trees, LSM trees)